Digital data encoding and decoding method and system
Digital data encoding and decoding method and system is provided. The data encoding includes encoding a frame signal into a bit stream, including detecting a specific bit pattern in the bit stream when the frame signal is present, generating a control signal in respect to the specific bit pattern, and encoding the bit stream into one or more marks and one or more spaces so that encoded data include a unique encoding pattern for the frame signal. The data decoding includes detecting at least one of mark and space from encoded data, recovering a bit stream from the encoded data when the at least one of mark and space is present, detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present, and recovering the frame signal from the encoded data.
1. A method for digital data communication, comprising:
encoding a frame signal into a bit stream, including:
detecting a specific bit pattern in the bit stream when the frame signal is present;
generating a control signal in respect to the specific bit pattern; and
encoding the bit stream into one or more marks and one or more spaces, so that encoded data include a unique encoding pattern for the frame signal in response to the control signal.
2. A method as claimed in claim 1 , wherein the step of encoding comprises:
modifying the bit stream based on a criteria to force the bit stream to contain the specific bit pattern.
3. A method as claimed in claim 2 , wherein the step of modifying comprises at least one of:
implementing inline modification so that the length of the bit stream is unchanged; and
toggling one or more bits to force the bit stream to contain the specific bit pattern.
4. A method as claimed in claim 2 , comprising:
counting, at a counter, the number of frames in which the specific bit pattern is not detected, the step of modifying being implemented when the counter reaches a threshold.
5. A method as claimed in claim 1 , wherein the step of encoding comprises:
inhibiting a transition in a Miller encoding, based on the control signal.
6. A method as claimed in claim 1 , wherein the specific bit pattern comprises a series of bits, each having a logic value.
7. A method as claimed in claim 1 , wherein the specific bit pattern is n bits long, wherein n is an integer greater than 1, and the number of frame signals to encode is n−1.
8. A method as claimed in claim 1 , further comprising:
decoding the encoded data, including:
recovering the bit stream from the encoded data; and
recovering the frame signal from the encoded data by detecting a pattern associated with the unique encoding pattern.
9. A method as claimed in claim 1 , wherein the step of generating comprises:
generating the control signal for triggering a code violation when the encoded data is decoded.
10. A system for digital data communication comprises:
an encoding circuit including:
a control unit for detecting a specific bit pattern in an incoming bit stream at a bit position relative to a frame signal and asserting a control signal in respect to the specific bit pattern; and
a mark and space unit for encoding the bit stream into one or more marks and one or more spaces so that the frame signal is embedded into encoded data, in response to the control signal.
11. A system as claimed in claim 10 , wherein the bit stream includes digital bits having logic values of 0 and 1, and wherein the mark and space unit employs a Miller encoding with the definition of 0 and 1 or a Miller encoding with the definition of 0 and 1 reversed.
12. A system as claimed in claim 11 , wherein the specific bit pattern comprises a series of bits, each having a logic value.
13. A system as claimed in claim 11 , wherein the specific bit pattern is n bits long, wherein n is an integer greater than 1, and the number of frame signals to encode is n−1.
14. A system as claimed in claim 10 , wherein the control unit comprises a state machine for controlling the operation of the control unit.
15. A system as claimed in claim 10 , wherein the control unit comprises:
a circuit for modifying the bit stream based on at least one of a state and configuration of the control unit to force the bit stream to contain the specific bit pattern.
16. A system as claimed in claim 15 , wherein the circuit for modifying implements inline modification so that the length of the bit stream is unchanged, toggling one or more bits to force the bit stream to contain the specific bit pattern, or a combination thereof.
17. A system as claimed in claim 15 , wherein the control unit comprises:
a counter for counting the number of frames in which the specific bit pattern is not detected, the control unit implements modification of the bit stream based on the output of the counter.
18. A system as claimed in claim 10 , wherein the control unit comprises:
a circuit for generating the control signal for inhibiting a transition in a Miller encoding.
19. A system as claimed in claim 18 , wherein the circuit for generating the control signal generates the control signal for triggering a code violation when the encoded data is decoded.
20. A system as claimed in claim 10 , further comprising:
a decoder including:
a recover for recovering the bit stream from the encoded data; and
a recover for recovering the frame signal from the encoded data.
21. A method for decoding comprising:
detecting at least one of mark and space from encoded data;
recovering a bit stream from the encoded data when the at least one of mark and space is present;
detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present; and
recovering the frame signal from the encoded data based on the specific bit pattern.
22. A method as claimed in claim 21 , further comprising:
providing a decoder clock with a first phase to recover the bit stream and the frame signal;
providing a decoder clock with a second phase to recover the bit stream and the frame signal; and
selecting either the bit stream and the frame signal recovered by using the decoder clock with the first phase, or the bit stream and the frame signal recovered by using the decoder clock with the second phase.
23. A system for decoding comprising:
a first decoder including:
a circuit for detecting at least one of mark and space from encoded data;
a first recover for recovering a bit stream from the encoded data when the at least one of mark and space is present;
a circuit for detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present; and
a second recover for recovering the frame signal based on the specific bit pattern.
24. A system as claimed in claim 23 , further comprising:
a second decoder corresponding to the first decoder, and
a circuit for selecting one of the outputs from the first decoder and the second decoder,
the first decoder and the second decoder receiving the encoded data, the first decoder and the second decoder using decoder clocks with different phases.