Double gate non-volatile memory device and method of manufacturing
View Patent ↗The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.
1. A non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a floating gate stack and a control gate;
the semiconductor channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region;
the floating gate stack being positioned in contact with one sidewall portion of the fin-shaped semiconductor channel region and between the source and drain regions, and being substantially perpendicular to the length direction (X) of the fin-shaped semiconductor channel region;
the control gate being in contact with the floating gate stack, wherein
an access gate is provided adjacent to the other sidewall portion of the fin-shaped semiconductor channel region and separated therefrom by only an intermediate gate oxide layer, and
wherein the floating gate stack comprises a set of layers which are parallel to the plane of the sidewall portion of the fin-shaped semiconductor channel region.
2. The non-volatile memory device according to claim 1 , wherein the set of layers of the floating gate stack comprise a first dielectric layer, a floating gate layer and a second dielectric layer; the floating gate layer being arranged for storing charge.
3. The non-volatile memory device according to claim 1 , wherein the set of layers of the floating gate stack comprise a first dielectric layer, a silicon nitride layer and a second dielectric layer; the silicon nitride layer being arranged for storing charge.
4. The non-volatile memory device according to claim 2 , wherein the floating gate layer is a spacer.
5. The non-volatile memory device according to claim 4 , wherein the second dielectric layer is a spacer.
6. The non-volatile memory device according to claim 1 , wherein the access gate comprises a semiconductor material or a metal.
7. The non-volatile memory device according to claim 1 , wherein the control gate comprises a semiconductor material or a metal.
8. The non-volatile memory device according to claim 3 , wherein the silicon nitride layer is a spacer.
9. The non-volatile memory device according to claim 8 , wherein the second dielectric layer is a spacer.
10. The non-volatile memory device according to claim 1 , wherein the access gate and the control gate are separated from the respective sidewalls of the fin-shaped semiconductor channel region by an unequal number of layers.
11. A method of manufacturing a non-volatile memory device on a substrate layer, the method comprising:
forming semiconductor source and drain regions;
forming a semiconductor channel region, the semiconductor channel region being fin-shaped and having two sidewall portions and a top portion, and extending between the source region and the drain regions;
forming a gate oxide layer covering the sidewalls and top portion of the fin-shaped semiconductor channel region;
forming a floating gate stack, the floating gate stack being positioned between the source and drain regions and being substantially perpendicular to the length direction of the fin-shaped semiconductor channel region, and
forming a control gate, the control gate being in contact with the floating gate stack, wherein the method further comprises
forming an access gate adjacent to one sidewall portion of the fin-shaped semiconductor channel region and separated from the fin-shaped semiconductor channel region by the gate oxide layer, and
wherein the floating gate stack is formed adjacent to and in contact with, the other sidewall portion of the fin-shaped semiconductor channel region; and
wherein forming the access gate comprises;
creating a line-shaped gate extending across the fin-shaped semiconductor channel region;
removing a top portion of the line-shaped gate from the top of the fin-shaped semiconductor channel region; and
removing a sidewall portion of the line-shaped gate from the sidewall of the fin-shaped semiconductor channel region that is opposite the access gate.
12. The method of manufacturing a non-volatile memory device according to claim 11 , wherein forming the floating gate stack comprises:
forming a first dielectric layer;
forming a floating gate layer, and
forming a second dielectric layer; the floating gate layer being arranged for storing charge.
13. The method of manufacturing a non-volatile memory device according to claim 12 , wherein the forming of the floating gate layer comprises the formation of a floating gate spacer.
14. The method of manufacturing a non-volatile memory device according to claim 11 , wherein forming the floating gate stack comprises:
forming a first dielectric layer;
forming a silicon nitride layer, and
forming a second dielectric layer; the silicon nitride layer being arranged for storing charge.
15. The method of manufacturing a non-volatile memory device according to claim 14 , wherein the forming of the silicon nitride layer comprises the formation of a silicon nitride spacer.
16. The method of manufacturing a non-volatile memory device according to claim 15 , wherein the forming of the second dielectric layer comprises the formation of a spacer of the second dielectric.