Method and apparatus for logic equivalence verification, and computer product
View Patent ↗A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.
1. A verifying apparatus comprising:
a merging unit that deletes a first flip-flop which is logically equivalent to a second flip-flop and merges the first flip-flop to the second flip-flop on a reference circuit and an implemented circuit respectively based on design data of the reference circuit and the implemented circuit which is logically equivalent to the reference circuit; and
a matching unit that matches the second flip-flop which remains after the merge process on the reference circuit and the second flip-flop on the implemented circuit according to name checking whether the name of the second flip-flop on the reference circuit and the name of the second flip-flop on the implemented circuit are identical, after the merging unit deletes and merges the first flip-flop, and
wherein the merging unit deletes and merges a plurality of the first flip-flops, among which is an upstream flip-flop having an output logic identical to an input logic of a downstream flip-flop.
2. The verifying apparatus according to claim 1 , wherein the merging unit adds a name of the first flip-flop to a name of the second flip-flop.
3. The verifying apparatus according to claim 1 , wherein the first flip-flop is driven by a clock signal that drives the second flip-flop.
4. The verifying apparatus according to claim 3 , wherein the first flip-flop is of a type having a data line with one input and one output.
5. The verifying apparatus according to claim 3 , wherein the first flip-flop is of a type identical to that of the second flip-flop.
6. The verifying apparatus according to claim 1 , further comprising a compressing unit that deletes a buffer or an even number of inverters between a plurality of the first flip-flops before the merging unit deletes and merges the first flip-flops.
7. A verifying method comprising:
deleting by a computer, a first flip-flop which is logically equivalent to a second flip-flop and merging the first flip-flop to the second flip-flop on a reference circuit and an implemented circuit respectively, based on design data of the reference circuit and the implemented circuit which is logically equivalent to the reference circuit; and
matching the second flip-flop on the reference circuit and the flip-flop which remains after the merge process on the implemented circuit according to name checking whether the name of the second flip-flop which remains after the merge process on the reference circuit and the name of the second flip-flop on the implemented circuit are identical, after the first flip-flop is merged at the merging, and
wherein the merging includes merging by deleting and merging a plurality of the first flip-flops, among which is an upstream flip-flop having an output logic identical to an input logic of a downstream flip-flop.
8. The verifying method according to claim 7 , wherein the merging includes merging by adding a name of the first flip-flop to a name of the second flip-flop.
9. The verifying method according to claim 7 , wherein the first flip-flop is driven by a clock signal that drives the second flip-flop.
10. The verifying method according to claim 9 , wherein the first flip-flop is of a type having a data line with one input and one output.
11. The verifying method according to claim 9 , wherein the first flip-flop is of a type identical to that of the second flip-flop.
12. The verifying method according to claim 7 , further comprising deleting a buffer or an even number of inverters between a plurality of the first flip-flops before the first flip-flops are merged at the merging.
13. A non-transitory computer-readable recording medium storing therein a computer program that causes a computer to execute an operation, comprising:
deleting a first flip-flop which is logically equivalent to second flip-flop and merging the first flip-flop to the second flip-flop on a reference circuit and an implemented circuit respectively, based on design data of the reference circuit and the implemented circuit which is logically equivalent to the reference circuit; and
matching the second flip-flop on the reference circuit and the flip-flop which remains after the merge process on the implemented circuit according to name checking whether the name of the second flip-flop which remains after the merge process on the reference circuit and the name of the second flip-flop on the implemented circuit are identical, after the first flip-flop is merged at the merging, and
wherein the merging includes merging by deleting and merging a plurality of the first flip-flops, among which is an upstream flip-flop having an output logic identical to an input logic of a downstream flip-flop.
14. The computer-readable recording medium according to claim 13 , wherein the merging includes merging by adding a name of the first flip-flop to a name of the second flip-flop.
15. The computer-readable recording medium according to claim 13 , wherein the first flip-flop is driven by a clock signal that drives the second flip-flop.
16. The computer-readable recording medium according to claim 15 , wherein the first flip-flop is of a type having a data line with one input and one output.
17. The computer-readable recording medium according to claim 15 , wherein the first flip-flop is of a type identical to that of the second flip-flop.
18. A verifying apparatus comprising:
a merging unit that deletes a first flip-flop which is logically equivalent to a second flip-flop and merges the first flip-flop to the second flip-flop on a reference circuit and an implemented circuit respectively based on design data of the reference circuit and the implemented circuit which is logically equivalent to the reference circuit; and
a matching unit that matches the second flip-flop which remains after the merge process on the reference circuit and the second flip-flop on the implemented circuit according to name checking whether the name of the second flip-flop on the reference circuit and the name of the second flip-flop on the implemented circuit are identical, after the merging unit deletes and merges the first flip-flop, and
wherein each of the second flip-flop on the reference circuit and the second flip-flop on the implemented circuit has a plurality of names one of which is a name of the first flip-flop deleted and merged to the second flip-flop, and
the matching unit matches each of the names of the second flip-flop on the reference circuit and each of the names of the second flip-flop on the implemented circuit, and checks whether any of the names of the second flip-flop on the reference circuit is identical to one of the names of the second flip-flop on the implemented circuit.