Non-volatile memory with high reliability
View Patent ↗A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.
1. A non-volatile memory system comprising:
a set of bit lines;
a set of non-volatile memory cells, each coupled to a common source and each including:
a non-volatile memory transistor having a control gate;
an access transistor having a gate, wherein the access transistor is connected between the non-volatile memory transistor and a corresponding one of the bit lines; and
a source select transistor having a gate, wherein the source select transistor is connected between the non-volatile memory transistor and the common source;
a word line coupled to the gate of each access transistor in the set of non-volatile memory cells;
a control gate line coupled to the control gate of each non-volatile memory transistor in the set of non-volatile memory cells;
a source select line coupled to the gate of each source select transistor in the set of non-volatile memory cells; and
means for performing a two-phase write operation to the set of non-volatile memory cells, wherein the two-phase write operation includes an erase phase and a program phase, wherein the means for performing the two-phase write operation comprise means for applying a first bit line voltage to a first subset of the set of bit lines during both the erase phase and the program phase, and means for applying a second bit line voltage, different than the first bit line voltage, to a second subset of the set of bit lines during both the erase phase and the program phase.
2. The non-volatile memory system of claim 1 , wherein the means for performing the two-phase write operation further comprise means for applying a first control voltage to the control gate line during the erase phase, and a second control voltage to the control gate line during the program phase, wherein the first control voltage is different than the second control voltage.
3. The non-volatile memory system of claim 2 , wherein the means for performing the two-phase write operation further comprise means for applying a common word line voltage to the word line during both the erase phase and the program phase.
4. The non-volatile memory system of claim 3 , wherein the means for performing the two-phase write operation further comprise means for applying a common source select voltage to the source select line during both the erase phase and the program phase.
5. A non-volatile memory system comprising:
a set of bit lines;
a set of non-volatile memory cells, each coupled to a common source and each including:
a non-volatile memory transistor having a control gate;
an access transistor having a gate, wherein the access transistor is connected between the non-volatile memory transistor and a corresponding one of the bit lines; and
a source select transistor having a gate, wherein the source select transistor is connected between the non-volatile memory transistor and the common source;
a word line coupled to the gate of each access transistor in the set of non-volatile memory cells;
a control gate line coupled to the control gate of each non-volatile memory transistor in the set of non-volatile memory cells; and
a source select line coupled to the gate of each source select transistor in the set of non-volatile memory cells; and
means for performing a two-phase write operation to the set of non-volatile memory cells, wherein the two-phase write operation includes an erase phase and a program phase, wherein the means for performing the two-phase write operation comprises means for inducing Fowler-Nordheim tunneling in a first subset of the set of non-volatile memory cells during the erase phase, and means for inducing Fowler-Nordheim tunneling in a second subset of the set of non-volatile memory cells during the corresponding program phase, wherein the first and second subsets are mutually exclusive.
6. The non-volatile memory system of claim 5 , wherein the means for performing the two-phase write operation inhibit Fowler-Nordheim tunneling in a third subset of the set of non-volatile memory cells during both the erase phase and the corresponding program phase.
7. The non-volatile memory system of claim 6 , wherein the first, second and third subsets are mutually exclusive and include all of non-volatile memory cells in the set of non-volatile memory cells.
8. The non-volatile memory system of claim 1 , wherein each access transistor, non-volatile memory transistor and source select transistor is an n-channel device.
9. The non-volatile memory system of claim 1 , wherein the means for performing the two-phase write operation further comprises means for applying a word line voltage to the word line, wherein the word line voltage is the same during both the erase phase and the program phase.
10. The non-volatile memory system of claim 9 , wherein the means for performing the two-phase write operation further comprises means for applying a source select voltage to the source select line, wherein the source select voltage is the same during both the erase phase and the program phase.
11. The non-volatile memory system of claim 1 , wherein a data bit having a first logic state is written to each non-volatile memory cell coupled to the first subset of the set of bit lines, and a data bit having a second logic state is written to each non-volatile memory cell coupled the second subset of the set of bit lines.
12. A non-volatile memory system comprising:
a plurality of bit lines;
a plurality of non-volatile memory cells, each coupled to a corresponding one of the plurality of bit lines and a common source, and each including a non-volatile memory transistor, an access transistor coupling the non-volatile memory transistor to the corresponding one of the plurality of bit lines, and a source select transistor coupling the non-volatile memory transistor to the common source; and
means for performing a two-phase write operation to the plurality of non-volatile memory cells, wherein the two-phase write operation includes an erase phase and a program phase, wherein the means for performing the two-phase write operation applies a first bit line voltage to a first subset of the plurality of bit lines during both the erase phase and the program phase, and applies a second bit line voltage, different than the first bit line voltage, to a second subset of the plurality of bit lines during both the erase phase and the program phase.
13. The non-volatile memory system of claim 12 , wherein the means for performing the two-phase write operation further applies a word line voltage to the access transistor in each of the plurality of non-volatile memory cells, wherein the word line voltage is the same during both the erase phase and the program phase.
14. The non-volatile memory system of claim 13 , wherein the means for performing the two-phase write operation further applies a source select voltage to the source select transistor in each of the plurality of non-volatile memory cells, wherein the source select voltage is the same during both the erase phase and the program phase.
15. The non-volatile memory system of claim 14 , wherein the means for performing the two-phase write operation further applies a first control voltage to the non-volatile memory transistor in each of the plurality of non-volatile memory cells during the erase phase, and a second control voltage to the non-volatile memory transistor in each of the plurality of non-volatile memory cells during the program phase, wherein the first control voltage is different than the second control voltage.
16. The non-volatile memory system of claim 12 , wherein a data bit having a first logic state is written to each non-volatile memory cell coupled to the first subset of the plurality of bit lines, and a data bit having a second logic state is written to each non-volatile memory cell coupled the second subset of the plurality of bit lines.
17. A non-volatile memory system comprising:
a plurality of bit lines;
a plurality of non-volatile memory cells, each coupled to a corresponding one of the plurality of bit lines and a common source, and each including a non-volatile memory transistor, an access transistor coupling the non-volatile memory transistor to the corresponding one of the plurality of bit lines, and a source select transistor coupling the non-volatile memory transistor to the common source; and
means for performing a two-phase write operation to the set of non-volatile memory cells, wherein the two-phase write operation includes an erase phase and a program phase, wherein the means for performing the two-phase write operation induce Fowler-Nordheim tunneling in a first subset of the plurality of non-volatile memory cells during the erase phase, and induce Fowler-Nordheim tunneling in a second subset of the plurality of non-volatile memory cells during the corresponding program phase, wherein the first and second subsets are mutually exclusive.
18. The non-volatile memory system of claim 17 , wherein the means for performing the two-phase write operation inhibit Fowler-Nordheim tunneling in a third subset of the plurality of non-volatile memory cells during both the erase phase and the corresponding program phase.
19. The non-volatile memory system of claim 18 , wherein the first, second and third subsets are mutually exclusive and include all of non-volatile memory cells in the plurality of non-volatile memory cells.