High voltage tolerant metal-oxide-semiconductor device
View Patent ↗A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.
1. Apparatus for increasing a voltage tolerance of a metal-oxide-semiconductor (MOS) device coupled to the apparatus, the apparatus comprising:
at least one capacitive element having a first capacitance value associated therewith, the at least one capacitive element having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and
a controller coupled to the at least one capacitive element, the controller being operative to adjust a ratio of the first capacitance value and a second capacitance value associated with the MOS device, wherein a second signal present at the gate of the MOS device is an attenuated version of the first signal, an amount of attenuation of the first signal being a function of the ratio of the first and second capacitance values.
2. The apparatus of claim 1 , wherein the at least one capacitive element comprises a programmable capacitor such that the first capacitance value is controllable as a function of a first control signal generated by the controller.
3. The apparatus of claim 1 , wherein the at least one capacitance element comprises a plurality of capacitors connected together in at least one of a series and a parallel arrangement, the controller being operative to adjust a ratio of respective capacitance values of the plurality of capacitors and the second capacitance value so as to control a voltage potential of the second signal present at the gate of the MOS device.
4. The apparatus of claim 1 , wherein the second capacitance value corresponds to a gate capacitance of the MOS device.
5. The apparatus of claim 1 , wherein the controller is operative to detect a magnitude of the first signal and to adjust the ratio of the first and second capacitance values as a function of the magnitude of the first signal.
6. The apparatus of claim 1 , wherein the controller is operative to adjust the first capacitance value relative to the second capacitance value to thereby control the ratio of the first and second capacitance values.
7. An integrated circuit including at least one apparatus according to claim 1 .
8. The apparatus of claim 1 , wherein the at least one capacitive element is coupled to a single terminal of the MOS device, said single terminal comprising the gate of the MOS device.
9. Apparatus for increasing a voltage tolerance of a metal-oxide-semiconductor (MOS) device coupled to the apparatus, the apparatus comprising:
at least one capacitive element having a first capacitance value associated therewith, the at least one capacitive element having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and
a controller coupled to the at least one capacitive element, the controller being operative to adjust the first capacitance value, wherein a second signal present at the gate of the MOS device is an attenuated version of the first signal, an amount of attenuation of the first signal being a function of a ratio of the first capacitance value and a second capacitance value associated with the MOS device.
10. The apparatus of claim 9 , wherein the at least one capacitive element comprises a programmable capacitor such that the first capacitance value is controllable as a function of a first control signal generated by the controller.
11. The apparatus of claim 9 , wherein the at least one capacitance element comprises a plurality of capacitors connected together in at least one of a series and a parallel arrangement, the controller being operative to adjust respective capacitance values of the plurality of capacitors so as to control a voltage potential of the second signal present at the gate of the MOS device.
12. The apparatus of claim 9 , wherein the second capacitance value corresponds to a gate capacitance of the MOS device.
13. The apparatus of claim 9 , wherein the controller is operative to detect a magnitude of the first signal and to adjust the first capacitance value as a function of the magnitude of the first signal.
14. An integrated circuit including at least one apparatus according to claim 9 .
15. The apparatus of claim 9 , wherein the at least one capacitive element is coupled to a single terminal of the MOS device, said single terminal comprising the gate of the MOS device.