Integrated circuit including vertical diode
View Patent ↗An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
1. An integrated circuit comprising:
a substrate including isolation regions;
a first conductive line formed in the substrate between isolation regions, the first conductive line comprising a single doping concentration and having a first polarity;
a vertical diode formed in the substrate, the vertical diode comprising a lightly doped region having a second polarity;
a highly doped region having the second polarity, the highly doped region directly contacting the lightly doped region of the vertical diode;
a silicide layer coupled to the highly doped region, the silicide layer aligned with the vertical diode in a direction perpendicular to the substrate;
a contact coupled to the silicide layer; and
a memory element coupled to the contact,
wherein the first conductive line provides a portion of the vertical diode.
2. The integrated circuit of claim 1 , wherein the first conductive line comprises an N+ word line,
wherein the lightly doped region comprises a P− region, and
wherein the highly doped region comprises a P+ region.
3. The integrated circuit of claim 1 , wherein the first conductive line comprises an N well.
4. The integrated circuit of claim 1 , wherein the vertical diode is self-aligned to the contact.
5. The integrated circuit of claim 1 , wherein the memory element comprises a resistivity changing material element.
6. The integrated circuit of claim 1 , wherein a P-N junction is formed at a boundary of the first conductive line.
7. A system comprising:
a host; and
a memory device communicatively coupled to the host, the memory device comprising:
a substrate including isolation regions;
a word line formed in the substrate between isolation regions, the word line comprising a single doping concentration and having a first polarity;
a vertical diode formed in the substrate, the vertical diode comprising a lightly doped region having a second polarity;
a highly doped region having the second polarity, the highly doped region directly contacting the lightly doped region of the vertical diode;
a silicide layer coupled to the highly doped region, the silicide layer aligned with the vertical diode in a direction perpendicular to the substrate;
a contact coupled to the silicide layer; and
a memory element coupled to the contact,
wherein the word line provides a portion of the vertical diode.
8. The system of claim 7 , wherein the memory device further comprises:
doped semiconductor regions separating the vertical diode from adjacent vertical diodes along the word line.
9. The system of claim 7 , wherein the memory device further comprises:
dielectric material isolation regions separating the vertical diode from adjacent vertical diodes along the word line.
10. The system of claim 7 , wherein the memory device further comprises:
doped semiconductor wells to electrically isolate the vertical diode from adjacent vertical diodes.
11. The system of claim 7 , wherein the memory device further comprises:
a write circuit configured to write data to the memory element;
a sense circuit configured to read data from the memory element; and
a controller configured to control the write circuit and the sense circuit.
12. A memory comprising:
a substrate including isolation regions;
an ion implanted word line formed in the substrate between isolation regions, the word line comprising a single doping concentration and having a first polarity;
an ion implanted vertical diode formed in the substrate, the vertical diode not a part of a transistor, and the vertical diode comprising a lightly doped region having a second polarity;
a highly doped region having the second polarity, the highly doped region directly contacting the lightly doped region of the vertical diode;
a silicide layer coupled to the highly doped region, the silicide layer aligned with the vertical diode in a direction perpendicular to the substrate;
a contact coupled to the silicide layer; and
a phase change memory element coupled to the contact,
wherein the word line provides a portion of the vertical diode.
13. The memory of claim 12 , wherein the word line comprises an N+ word line,
wherein the lightly doped region comprises a P− region, and
wherein the highly doped region comprises a P+ region.
14. The memory of claim 12 , wherein the word line comprises an N well.
15. The memory of claim 14 , further comprising:
P wells,
wherein the word line is isolated from adjacent word lines via the isolation regions and the P wells.
16. An integrated circuit comprising:
a substrate including isolation regions;
a first conductive line formed in the substrate between isolation regions, the first conductive line comprising a single doping concentration and having a first polarity;
a first vertical diode formed in the substrate, the first vertical diode comprising a first lightly doped region and having a second polarity;
a second vertical diode formed in the substrate, the second vertical diode comprising a second lightly doped region and having the second polarity;
a first highly doped region having the second polarity, the first highly doped region directly contacting the first lightly doped region of the first vertical diode;
a second highly doped region having the second polarity, the second highly doped region directly contacting the second lightly doped region of the second vertical diode;
a first silicide layer coupled to the first highly doped region, the first silicide layer aligned with the first vertical diode in a direction perpendicular to the substrate;
a second silicide layer coupled to the second highly doped region, the second silicide layer aligned with the second vertical diode in the direction perpendicular to the substrate;
a first contact coupled to the first silicide layer;
a second contact coupled to the second silicide layer;
a first memory element coupled to the first contact;
a second memory element coupled to the second contact,
wherein the first conductive line provides a portion of the first vertical diode and the second vertical diode,
wherein the first lightly doped region directly contacts the first conductive line, and
wherein the second lightly doped region directly contacts the first conductive line.
17. The integrated circuit of claim 16 , wherein the first conductive line comprises an N+ word line,
wherein the first lightly doped region comprises a P− region,
wherein the second lightly doped region comprises a P− region,
wherein the first highly doped region comprises a P+ region, and
wherein the second highly doped region comprises a P+ region.
18. The integrated circuit of claim 16 , wherein the first vertical diode is self-aligned to the first contact, and
wherein the second vertical diode is self-aligned to the second contact.
19. The integrated circuit of claim 16 , wherein the first memory element comprises a first resistivity changing material element, and
wherein the second memory element comprises a second resistivity changing material element.