Adaptive electrostatic discharge (ESD) protection of device interface for local interconnect network (LIN) bus and the like
View Patent ↗Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.
1. An integrated circuit device having adaptive electrostatic discharge (ESD) protection and noise signal rejection, comprising:
an external connection adapted for connection to a data bus;
a data bus interface coupled to the external connection;
a circuit function coupled to the data bus interface;
an ESD protection circuit coupled to the external connection and a common of the integrated circuit device;
an ESD enhancement capacitor coupled to the external connection;
an ESD capacitor control, wherein the ESD capacitance control couples the ESD enhancement capacitor into the ESD protection circuit when an input of the ESD capacitor control is at a first voltage, and decouples the ESD enhancement capacitor from the ESD protection circuit when the input of the ESD capacitor control is at a second voltage;
a high pass filter coupled to the external connection, wherein the high pass filter passes high frequency noise signals but not low frequency data signals; and
a signal amplitude detector coupled to the high pass filter, wherein when the high frequency noise signals are present on the external connection the signal amplitude detector applies the second voltage to the ESD capacitor control, and when there are substantially no high frequency noise signals are on the external connection the signal amplitude detector applies the first voltage to the ESD capacitor control.
2. The integrated circuit device of claim 1 , wherein the data bus interface is a data bus receiver.
3. The integrated circuit device of claim 1 , wherein the data bus interface is a data bus driver.
4. The integrated circuit device of claim 1 , wherein the data bus interface is a data bus driver and receiver.
5. The integrated circuit device of claim 1 , wherein the high frequency noise signals are direct power injection (DPI) signals.
6. The integrated circuit device of claim 1 , wherein the high frequency noise signals are electromagnetic interference (EMI) signals.
7. The integrated circuit device o f claim 1 , wherein the ESD protection circuit comprises a first metal oxide semiconductor (MOS) device.
8. The integrated circuit device of claim 7 , wherein the first MOS device is configured having a substantially grounded gate.
9. The integrated circuit device of claim 1 , wherein the ESD capacitor control comprises a second metal oxide semiconductor (MOS) device having a gate coupled to the an output of the signal amplitude detector.
10. The integrated circuit device of claim 1 , wherein the signal amplitude detector delays the second voltage after detecting the high frequency noise signals on the external connection.
11. The integrated circuit device of claim 1 , wherein the signal amplitude detector comprises a signal detection diode and a low pass filter.
12. The integrated circuit device of claim 1 , wherein the circuit function is a digital logic function.
13. The integrated circuit device of claim 1 , wherein the circuit function is an analog circuit function.
14. The integrated circuit device of claim 1 , wherein the circuit function is a mixed signal circuit function.
15. The integrated circuit device of claim 1 , wherein the ESD capacitor control comprises a metal oxide semiconductor (MOS) device and a low value resistor, the ESD enhancement capacitor is connected to the low value resistor, wherein the MOS device decouples the low value resistor and the ESD enhancement capacitor from the ESD protection circuit when the input of the ESD capacitor control is at the second voltage.
16. The integrated circuit device of claim 15 , the ESD enhancement capacitor is decoupled from the ESD protection circuit when the MOS device couples the low value resistor and ESD enhancement capacitor to the common of the integrated circuit device.
17. The integrated circuit device of claim 1 , wherein the ESD capacitor control comprises a metal oxide semiconductor (MOS) device, a bipolar transistor and a low value resistor, the ESD enhancement capacitor is connected to the low value resistor, wherein the bipolar transistor decouples the low value resistor and the ESD enhancement capacitor from the ESD protection circuit when the input of the ESD capacitor control is at the second voltage.
18. The integrated circuit device of claim 1 , further comprising a diode coupled between the external connection and the ESD enhancement capacitor and the ESD capacitor control.
19. The integrated circuit device of claim 18 , wherein the diode is a vertical PNP device formed during fabrication of the integrated circuit device.
20. The integrated circuit device of claim 1 , wherein the data bus is a Local Interconnect Network (LIN) bus.
21. The integrated circuit device of claim 1 , wherein the data bus is a Controller Area Network (CAN) bus.