Method of forming isolation regions for integrated circuits

1. A method of manufacturing an integrated circuit having trench isolation regions in a substrate including germanium, the method comprising:

forming a mask layer above the substrate;

selectively etching the mask layer to form apertures associated with locations of the trench isolation regions;

forming trenches in the substrate at the locations;

providing a semiconductor or metal layer within the trenches and in direct contact with the substrate in a low temperature atomic layer deposition process; and

forming oxide liners in contact with the substrate using the semiconductor or metal layer in the trenches of the substrate.

2. The method of claim 1 , further comprising providing an insulative material in the trenches to form the trench isolation regions.

3. The method of claim 2 , further comprising removing the insulative material until the mask layer is reached.

4. The method of claim 1 , wherein the semiconductor or metal layer is amorphous silicon.

5. The method of claim 1 , wherein the low temperature process is performed at a temperature of approximately 700° C. or less.

6. The method of claim 1 , wherein the semiconductor or metal layer includes non-amorphous semiconductor material.

7. The method of claim 1 , wherein the atomic layer deposition process utilizes a pulse cycle process.

8. The method of claim 1 , wherein the forming oxide liners step is an oxidation process.

9. A method of forming shallow trench isolation regions in a first semiconductor layer, the method comprising:

providing a hard mask layer above the first semiconductor layer;

providing a photoresist layer above the hard mask layer;

selectively removing portions of the photoresist layer at locations in a photolithographic process;

removing the hard mask layer at the locations;

forming trenches in the hard mask layer under the locations;

providing a conformal semiconductor layer in the trenches and in direct contact with the first semiconductor layer in an atomic layer deposition process at a temperature of approximately 700° C. or less; and

converting the conformal semiconductor layer into an oxide liner in the trenches, the oxide liner in contact with the first semiconductor layer.

10. The method of claim 9 , further comprising:

providing a pad oxide layer above a strained silicon layer before the providing a hard mask layer step.

11. The method of claim 10 further comprising:

removing the pad oxide layer at the locations before the forming trenches step.

12. The method of claim 9 , further comprising:

providing an insulative material in the trenches to form the shallow trench isolation regions; and

removing the hard mask layer in a wet bath.

13. The method of claim 12 , wherein the wet bath includes acid.

14. The method of claim 9 , wherein conformal semiconductor layer comprises non-amorphous silicon.

15. The method of claim 14 , wherein the oxide liner is silicon dioxide grown in an oxygen atmosphere.

16. The method of claim 9 , wherein the atomic layer deposition process utilizes a pulse cycle process.

17. A method of forming a liner in a trench in a germanium containing layer, the method comprising:

selectively etching the germanium containing layer to form the trench;

providing a semiconductor layer in the trench and in direct contact with the germanium containing layer in a low temperature atomic layer deposition process; and

forming an oxide liner from the semiconductor layer, the oxide liner in contact with the germanium containing layer.

18. The method of claim 17 , wherein the low temperature atomic layer deposition process is performed at a temperature of approximately 700° C. or less.

19. The method of claim 17 , wherein the semiconductor layer in the trench comprises non-amorphous silicon.

20. The method of claim 19 , wherein the oxide liner is 200-500 Å thick.