Memory system and method
In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.
1. An apparatus, comprising:
a memory controller configured to control first and second memory components;
a point-to-point data bus configured to pass data between the memory controller and the memory components, the point-to-point data bus having a direct connection from each memory component to the memory controller; and
a daisy chained address bus configured to pass commands between the memory controller and the memory components, the address bus having a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component,
wherein each memory component has a data interface connected to the point-to-point data bus, wherein if the apparatus is set to depth expansion a portion of each data interface is de-powered while the memory components exchange data with the memory controller over the data bus, wherein if the apparatus is not set to depth expansion the entire data interfaces are powered while the memory components exchange data with the memory controller over the data bus.
2. The apparatus of claim 1 , wherein the first memory component further comprises:
a receiver connected to the address bus, the receiver configured to communicate with the memory controller over the direct connection of the address bus;
a transmitter connected to the address bus, the transmitter configured to communicate with the second memory component over the daisy chain connection of the address bus; and
circuitry configured to internally link the first memory component receiver and the first memory component transmitter such that all commands received via the receiver are retransmitted using the transmitter.
3. The apparatus of claim 2 , wherein all the commands are re-transmitted independently of whether the received address command corresponds to an address location of the second memory component.
4. The apparatus of claim 1 , wherein a count of active pins of a data interface of the memory controller is greater than a count of active pins of the data interface of one of the memory components.
5. The apparatus of claim 4 , wherein the count of active pins of the data interface of the memory controller is equal to the combined count of active pins of every connected memory component.
6. The apparatus of claim 1 , wherein the point-to-point data bus is a serial bus.
7. An apparatus, comprising:
a memory controller configured to control first and second memory components;
a point-to-point data bus configured to pass data between the memory controller and the memory components, the point-to-point data bus having a direct connection from each memory component to the memory controller; and
a daisy chained address bus configured to pass commands between the memory controller and the memory components, the address bus having a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component,
wherein the memory controller has N memory components coupled thereto over the daisy chain address bus, and each memory component has a data interface connected to the data bus, wherein each data interface has 1/Nth the bit width of the memory controller, and the memory controller circuitry configured to set a memory system depth, the circuitry to cause the memory controller to distribute a data word to be written over both memory components if the memory controller is set to depth expansion, the circuitry to cause the memory controller to write the data word to a single one of the memory components if the memory controller is not set to depth expansion.
8. An apparatus, comprising:
a memory controller configured to control first and second memory components;
a point-to-point data bus configured to pass data between the memory controller and the memory components, the point-to-point data bus having a direct connection from each memory component to the memory controller; and
a daisy chained address bus configured to pass commands between the memory controller and the memory components, the address bus having a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component,
wherein the memory controller has N memory components coupled thereto over the daisy chain address bus, and each memory component has a data interface connected to the data bus, wherein each data interface has 1/Nth the bit width of the memory controller, and the memory controller circuitry configured to set a memory system width, the circuitry to cause the memory controller to exchange data through a first portion of a local data interface if the memory controller is set to width expansion, the circuitry to cause the memory controller to exchange data through a second smaller portion of the local data interface if the memory controller is not set to width expansion.
9. A local data storage component, comprising:
a data interface configured to directly connect to a memory controller via a point-to-point data bus, the data interface connected directly to the memory controller independently of any intermediary devices;
a command receive interface configured to receive commands via an address bus;
a command transmit interface configured to connect to a remote data storage component; and
circuitry configured to pass the commands received over the receive interface to the transmit interface for re-transmission to the remote data storage component;
wherein the remote data storage component has a data interface connected to the point-to-point data bus, and wherein if the memory controller is set to depth expansion a portion of each data interface is de-powered while the data storage components exchange data with the memory controller over the data bus, and if the memory controller is not set to depth expansion the entire data interfaces are powered while the data storage components exchange data with the memory controller over the data bus.
10. The local data storage component of claim 9 , wherein the circuitry is configured to pass the commands independently of which data storage component the commands correspond to.
11. The local data storage component of claim 9 , wherein the data interface has a first bit width and the local data storage component is configured to operate with a memory controller having a second bit width that is larger than the first bit width.
12. The local data storage component of claim 9 , wherein the local data storage component is configured to read stored data or write received data according to the retransmitted command.
13. The local data storage component of claim 9 , wherein the local data storage component is configured to operate on data comprising a fraction of a word width of data operated on by the memory controller.
14. A method, comprising:
connecting a plurality of memory components in series on a memory controller's address bus, the initial memory component in the series to receive all commands sent from the memory controller and for the memory components;
connecting a data interface on each of the plurality of memory components to the memory controller through a plurality of data buses; and
if the memory controller is set to depth expansion de-powering a portion of each data interface while the memory components exchange data with the memory controller over the data bus;
if the memory controller is not set to depth expansion powering the entire data interfaces while the memory components exchange data with the memory controller over the data bus,
such that each memory component can receive data to be written independently of the other memory components.
15. The method of claim 14 , further comprising configuring the memory components to propagate received commands such that every memory component receives the same commands received by all of the other memory components.
16. The method of claim 15 , further comprising:
configuring the memory components to impose programmable delays to align received data with received commands;
wherein the memory components are configured to impose different, progressively larger delays staring with an initial memory component of the series being configured to impose the least delay and ending with the last memory component of the series being configured to impose the greatest delay.
17. The method of claim 14 , wherein the pin count of each memory component is less than the pin count of the memory controller.
18. The method of claim 17 , wherein each of the data buses are connected to a different subset of data pins on a data interface of the memory controller.