Lock and key through-via method for wafer level 3 D integration and structures produced
View Patent ↗A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
1. A structure comprising two device layers joined together to form an electronic system and further comprising:
a first device layer disposed on a first substrate and comprising a first set of circuits and interconnect wiring;
a second device layer disposed on a second substrate and comprising a second set of circuits and interconnect wiring;
said first and said second device layers further connected using two sets of via connections comprising a first set of via connections that extend from below the top surface of said first device layer to the top surface of said second device layer and a second set of via connections that extend from said top surface of said first device layer through said second device layer, said second substrate and connecting to interconnect layers and input output terminals disposed on the back side of said second substrate;
said structure further comprising an adhesive layer disposed between said top surface of said first device layer and said top surface of said second device layer and surrounding a portion of the height of said first and said second via connections; and
further comprising an passivation coating to protect the sidewalls of said first and second sets of vias in said portions where they are surrounded by said adhesive layer.
2. A structure according to claim 1 further comprising at least one more device layer in the manner of said second device layer, stacked on and attached to the back side of said second device layer and connected to said first and said second device layers and said input output terminal by means of additional via connections.
3. A structure according to claim 1 wherein said circuits in said first and second device layer comprise any one of logic circuits, memory circuits, controller circuits, image processing circuits, optoelectronic circuits and combinations thereof.
4. A structure according to claim 1 wherein said interconnect layers in said second device layer comprise dual damascene wiring and vias, through substrate vias and combinations thereof.
5. A structure according to claim 1 wherein said first and second substrates comprise silicon, or gallium arsenide, or silicon carbide.
6. A structure according to claim 1 wherein said adhesive layer comprises a polyimide adhesive, or benzocyclobutene adhesive, or polyarylene ether adhesive, or epoxy adhesive.
7. A structure according to claim 1 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.