Granted Patent B1

US 8,703,001 · App. 12/244,681 · Granted Apr 22, 2014

Abstract

Claims (43)

1. A method for etching at least a first set of wafers and a second set of wafers, the method comprising:

providing an electrically negative grid member that is electrically negative relative to a reference;

providing an electrically positive grid member that is electrically positive relative to the reference;

disposing the electrically negative grid member with respect to the electrically positive grid member such that a first space exists between the electrically negative grid member and the electrically positive grid member;

providing an electrically grounded grid member to be the reference;

configuring the electrically grounded grid member such that the ground grid member is thicker than at least one of the electrically negative grid member and the electrically positive grid member;

disposing the electrically negative grid member between the electrically grounded grid member and the electrically positive grid member;

determining a first size for the first space;

etching the first set of wafers with the first space configured to have the first size, wherein the electrically negative grid member is maintained apart from the electrically positive grid member by a first plurality of insulating connecting mechanisms defining the first size while etching the first set of wafers with the first space configured to have the first size, at least a subset of the first plurality of insulating connecting mechanisms being disposed throughout an interior region of the electrically negative grid member;

determining a second size for the first space; and

etching the second set of wafers with the first space configured to have the second size, the first size being larger than the second size, the first set of wafers requiring higher etch uniformity than the second set of wafers, wherein the electrically negative grid member is maintained apart from the electrically positive grid member by a second plurality of insulating connecting mechanisms defining the second size, the second plurality of insulating connecting mechanism substituting for the first plurality of insulating connecting mechanisms while etching the first set of wafers with the first space configured to have the second size, at least a subset of the second plurality of insulating connecting mechanisms being disposed throughout the interior region of the electrically negative grid member,

wherein the first space between the electrically negative grid member and the electrically positive grid member is greater in dimension than a second space between the electrically negative grid member and the electrically grounded grid member.

2. The method of claim 1 , further comprising:

monitoring etch uniformity when etching the first set or wafers; and

adjusting the first space from having the first size to having the second size after the etch uniformity has decreased to a predetermined threshold,

wherein the first set of wafers is etched before the second set of wafers is etched.

3. The method of claim 1 further comprising:

monitoring etch uniformity when etching the first set of wafers; and

replacing the first set of connecting mechanisms with the second set of connecting mechanisms when the etch uniformity decreases to a predetermined threshold.

4. The method of claim 1 wherein the first size is in a range of 0.055 inch to 0.110 inch, and the second size is a range of 0.030 inch to 0.075 inch.

5. The method or claim 1 further comprising configuring the electrically grounded grid member such that the ground grid member is thicker than both the electrically negative grid member and the electrically positive grid member.

6. A method for etching a first set of wafers, the method comprising:

providing an electrically grounded grid member;

providing an electrically negative grid member that is electrically negative relative to the grounded grid member; and

providing an electrically positive grid member that is electrically positive relative to the grounded grid member,

wherein a first space exists between the electrically negative grid member and the electrically positive grid member,

wherein a second space exists between the electrically negative grid member and the electrically grounded grid member,

wherein the electrically negative grid member is maintained apart from the electrically positive grid member by a first plurality of insulating connecting mechanisms having a first dimension that defines the first space, at least a subset of the first plurality of insulating connecting mechanisms being disposed throughout an interior region of the electrically negative grid member,

wherein the electrically negative grid member is maintained apart from the electrically grounded grid member by a second plurality of insulating connecting mechanisms having a second dimension that defines the second space, at least a subset of the second plurality of insulating connecting mechanisms being disposed throughout an interior region of the electrically grounded grid member,

wherein the first space has a greater dimension than the second space, and

wherein the grounded grid member is thicker than at least one of the electrically negative grid member and the electrically positive grid member.

7. The method of claim 6 wherein the set of connecting mechanisms further determining at least a size of the first space.

8. The method of claim 6 wherein the electrically grounded grid member is thicker than both the electrically negative grid member and the electrically positive grid member.

9. The method of claim 6 wherein a width of the first space is at least 0.030 inch, and a width of the second space is at least 0.055 inch.

10. The method of claim 6 wherein a width of the second space is between 0.055 inch and 0.110 inch.

11. The method of claim 6 wherein the width of the first space is between 0.030 inch and 0.075 inch.

12. The method of claim 6 further including providing a wafer support mechanism for supporting a wafer of the first set of wafers, the electrically grounded grid member being disposed closer to the wafer support member than the electrically negative grid member, electrically negative grid member being disposed closer to the wafer support member than the electrically positive grid member.

13. The method of claim 12 further including providing an ion chamber for containing charged particles, the electrically grounded grid member, the electrically negative grid member, and the electrically positive grid member being disposed between the ion chamber and the wafer support mechanism.

14. The method of claim 13 further including providing a radio frequency coil for exciting gas in the ion chamber to generate ions for etching the first set of wafers.

15. The method of claim 14 wherein each of the electrically grounded grid member, the electrically negative grid member, and the electrically positive grid member include a second set of holes for allowing the ions to flow from the ion chamber into a processing chamber.

16. The method of claim 15 further including providing a support ring configured for providing structure support to at least one of the electrically grounded grid member, the electrically negative grid member, and the electrically positive grid member.

17. The method of claim 16 further including providing an adjustment mechanism for adjusting at least one of the first space and the second space by replacing the connecting mechanisms.

18. The method of claim 17 further including providing a monitoring mechanism for determining the etch uniformity during substrate processing.

Assignments (17)