Electron blocking layers for electronic devices
View Patent ↗Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.
1. A gate stack of a memory device, the gate stack comprising:
a charge storage layer comprising localized charge traps on a tunneling dielectric layer;
a first dielectric layer comprising a first oxynitride having a first dielectric constant directly on the charge storage layer;
a second dielectric layer comprising an oxide having a second dielectric constant directly on the first dielectric layer; and
a third dielectric layer comprising a second oxynitride having a third dielectric constant directly on the second dielectric layer,
wherein the first and third dielectric constants are greater than the second dielectric constant.
2. The gate stack of claim 1 , wherein the memory device exhibits a charge loss of about 5 V or less over a period of 24 hours at a temperature of 250° C.
3. The gate stack of claim 1 , wherein the second dielectric layer has a thickness of from about 8 nm to about 16 nm.
4. The gate stack of claim 1 , wherein each of the first and third dielectric layers has a thickness of from about 1 nm to about 6 nm.
5. The gate stack of claim 1 , wherein the first and third dielectric layers comprise at least one of hafnium oxynitride and silicon oxynitride.
6. The gate stack of claim 1 , wherein the second dielectric layer comprises aluminum oxide.
7. The gate stack of claim 1 , wherein the localized charge traps are metal nanocrystals.
8. The gate stack of claim 1 , wherein the first dielectric layer includes a lower concentration of nitrogen than the third dielectric layer.
9. The gate stack of claim 1 , wherein the memory device exhibits a charge retention of about 85% or greater over a period of 24 hours at a temperature of 250° C.
10. The gate stack of claim 9 , wherein the memory device exhibits a charge retention of about 90% or greater over the period of 24 hours at the temperature of 250° C.
11. A gate stack of a memory device, the gate stack comprising:
a charge storage layer comprising polysilicon on a tunneling dielectric layer;
a first dielectric layer comprising a first oxynitride having a first dielectric constant directly on the charge storage layer;
a second dielectric layer comprising an oxide having a second dielectric constant directly on the first dielectric layer; and
a third dielectric layer comprising a second oxynitride having a third dielectric constant directly on the second dielectric layer,
wherein the first and third dielectric constants are greater than the second dielectric constant, and wherein the memory device exhibits a charge retention of about 85% or greater over a period of 24 hours at a temperature of 250° C.