IP Library Granted Patent US 7,974,805
Granted Patent B2
US 7,974,805 · App. 12/251,414 · Granted Jul 5, 2011

Image sensor and method

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Quick Facts
Patent No.
US 7,974,805
App. No.
12/251,414
Granted
Jul 5, 2011
Kind
B2
Abstract

Described herein are methods that may improve yield of an image sensor. In one embodiment, a method that may improve yield of an image sensor includes generating output values of control logic associated with an array of light sensitive elements. The method further may include determining if the control logic has one or more faulty output values. The method further may include automatically correcting the one or more faulty output values.

Claims (36)

1. A method to improve yield of an image sensor, the method comprising:

selecting a pixel block from a plurality of pixel blocks of the image sensor, wherein each of the plurality of pixel blocks of the image sensor is associated with a control logic and a majority voting circuit;

generating output values of the control logic associated with the selected pixel block having an array of light sensitive elements in response to input data;

determining if the control logic has one or more faulty output values by the majority voting circuit associated with the selected pixel block, wherein the majority voting circuit is coupled with the control logic associated with the selected pixel block and neighboring control logics associated with neighboring pixel blocks of the selected pixel block; and

automatically correcting the one or more faulty output values.

2. The method of claim 1 , further comprising:

providing light to the array of light sensitive elements of the selected pixel block.

3. The method of claim 2 , further comprising:

automatically generating an image based on the control logic having no faulty output values.

4. The method of claim 1 , wherein the majority voting circuit determines if the control logic has one or more faulty output values by comparing each output value generated by the control logic to one or more neighbor output values generated by the neighboring control logics.

5. The method of claim 4 , wherein the majority voting circuit determines if the control logic has one or more faulty output values by comparing an output value i to output values i+1 and i−1 with i being an integer number.

6. An image sensor, comprising:

a plurality of sections, wherein each section of the plurality of sections comprising:

a pixel block having an array of light sensitive elements;

a control logic coupled to the array of light sensitive elements of the pixel block, wherein the control logic is configured to generate output values in response to input data; and

a fault detection circuit coupled to the control logic and neighboring control logics of neighboring pixel blocks of the pixel block to automatically determine if the control logic has one or more faulty output values, wherein the fault detection circuit is configured to automatically correct the one or more faulty output values and to generate corrected output values.

7. The image sensor of claim 6 , further comprising:

control lines to receive the corrected output values from the fault detection circuit.

8. The image sensor of claim 7 , wherein the corrected output values are used to select the light sensitive elements.

9. The image sensor of claim 6 , wherein the control logic comprises at least one of shift registers, flip-flops, and address decoders.

10. The image sensor of claim 6 , wherein the fault detection circuit determines if the control logic has one or more faulty output values by comparing each output value generated by the control logic to one or more neighbor output values generated by the neighboring control logics.

11. The image sensor of claim 6 , wherein the fault detection circuit comprises a majority voting circuit.

12. The image sensor of claim 11 , wherein the majority voting circuit determines if the control logic has one or more faulty output values by comparing an output value i received from control logic i to output values i+1 and i−1 received from control logic i+1 and i−1, respectively, with i being an integer number.

13. The image sensor of claim 6 , wherein the light sensitive elements are passive or active pixels sensors.

14. The image sensor of claim 6 , wherein the control logic is embedded in the array of light sensitive elements in a stitched pattern.

15. The image sensor of claim 6 , further comprising:

read out circuitry coupled to the array of light sensitive elements, the read out circuitry to read out pixel values for the image sensor.

16. An apparatus to automatically improve yield of an image sensor, comprising:

means for selecting a pixel block from a plurality of pixel blocks of the image sensor, wherein each of the plurality of pixel blocks of the image sensor is associated with a control logic and a majority voting circuit;

means for generating output values of the control logic associated with the selected pixel block having an array of light sensitive elements in response to input data;

means for determining if the control logic has one or more faulty output values by the majority voting circuit associated with the selected pixel block, wherein the majority voting circuit is coupled with the control logic associated with the selected pixel block and neighboring control logics associated with neighboring pixel blocks of the selected pixel block; and

means for automatically correcting one or more faulty output values.

17. The apparatus of claim 16 , further comprising:

means for providing light to the array of light sensitive elements of the selected pixel block;

means for automatically generating an image based on the control logic having no faulty output values.

18. The apparatus of claim 16 , further comprising a fault detection circuit to determine if the control logic has the one or more faulty output values by comparing each output value to one or more neighbor output values.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2012
From: ON SEMICONDUCTOR TRADING, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 028447/0926 →
CONFIRMATORY ASSIGNMENT Recorded Mar 23, 2011
From: CYPRESS SEMICONDUCTOR CORPORATION
To: ON SEMICONDUCTOR TRADING LTD.
Reel/Frame 026004/0167 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2008
From: SCHEFFER, DANNY
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 021706/0500 →