IP Library Granted Patent US 8,637,986
Granted Patent B2
US 8,637,986 · App. 12/256,333 · Granted Jan 28, 2014

Semiconductor device and method for manufacturing thereof

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Quick Facts
Patent No.
US 8,637,986
App. No.
12/256,333
Granted
Jan 28, 2014
Kind
B2
Abstract

A semiconductor device which includes a first semiconductor chip 10 , a first electrode 12 formed on the first semiconductor chip 10 , a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24 , which is formed on the second semiconductor chip 20 , and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24 , and a method for manufacturing thereof are provided.

Claims (17)

1. A semiconductor device comprising:

a semiconductor chip;

a first electrode formed on the semiconductor chip;

a first material layer to which the semiconductor chip is mounted;

a second material layer;

a second semiconductor chip;

a second electrode formed on the second semiconductor chip having a protrusion formed therein wherein the second electrode and material formed inside of the protrusion to have slanted side surfaces have coplanar bottom surfaces, wherein a bottom surface of said material and a top surface of said material are parallel and said top surface is shorter in length than said bottom surface and wherein the protrusion of the second electrode is centered halfway between a pair of protrusions of the first electrode that extend in the direction toward the second electrode; and

a bonding terminal for bonding the first electrode and the second electrode.

2. The semiconductor device according to claim 1 , wherein the first electrode and second electrode are bonded to cover at least part of a side surface of the protrusion.

3. The semiconductor device according to claim 1 , wherein the bonding terminal is formed from a solder.

4. The semiconductor device according to claim 1 , wherein:

the bonding terminal is formed from a metal post and a solder layer; and

the solder layer is formed on a surface of the metal post opposite to the second electrode.

5. The semiconductor device according to claim 1 , wherein:

the semiconductor chip includes a material layer;

the material layer is disposed at a lower portion of the protrusion; and

the material layer has a thermal conductivity lower than that of a surface of the second electrode.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 041175/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040908/0960 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2016
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 040165/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2009
From: MASUDA, NAOMI; HOSHINO, MASATAKA; FUKUYAMA, RYOTA
To: SPANSION LLC
Reel/Frame 022338/0607 →