METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE
The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
1 . A semiconductor device, comprising:
a bipolar transistor region, including bipolar transistors having:
a silicon/germanium (SiGe) layer located over a collector tub;
a first dielectric layer located over the collector tub and adjacent either side of the SiGe layer;
a polysilicon layer located over the SiGe layer and the dielectric layer;
a second dielectric layer located over the polysilicon layer;
a protective layer located over the dielectric layer, wherein the protective layer has a weight percent of hydrogen that is less than about 9%; and
an emitter layer located over the protective layer; and
a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.
2 . The device recited in claim 1 , wherein the protective layer is a silicon oxynitride stack.
3 . The device recited in claim 1 , wherein a portion of the dielectric layer is located between the protective layer and the polysilicon layer.
4 . The device recited in claim 3 , further including a silicon nitride layer located between the polysilicon layer and the emitter.
5 . The device recited in claim 1 , wherein the protective layer is resistive to a hydrofluoric clean.
6 . The device recited in claim 5 , wherein the protective layer comprises oxides, nitrides, or combinations thereof.
7 . The device recited in claim 1 , wherein the semiconductor device is an integrated circuit and further includes dielectric layers located over the bipolar transistor region and the non-bipolar transistor region and interconnects located over and within the dielectric layers that interconnect the bipolar transistors and the non-bipolar transistors.
8 . The device recited in claim 1 , wherein a threshold voltage of the bipolar transistors ranges from about 2.7 volts to about 3.25 volts.
9 . The device recited in claim 8 , wherein the bipolar transistors are NPN bipolar transistors.
10 . The device recited in claim 1 , wherein the first dielectric layer has a cavity formed therein filled with the SiGe, the polysilicon layer having an emitter opening formed therein, the protective layer is partially located within the emitter opening and along the sidewalls of the emitter opening and wherein the second dielectric is partially located in the emitter opening.
11 . The device recited in claim 10 wherein, the protective layer is a first protective layer and the device further includes a second protective layer partially located within the emitter opening and a portion of the dielectric layer is located between the first and second protective layers.
12 . The device recited in claim 11 , wherein the second protective layer has a weight percent of hydrogen that is less than about 9%.
13 . The device recited in claim 11 , wherein the emitter is located on the second protective layer located along the sidewalls of the emitter opening.
14 . The device recited in claim 10 , wherein the protective layer is selective to silicon germanium (SiGe), such that SiGe does is not located on the protective layer.