IP Library Granted Patent US 7,718,471
Granted Patent B1
US 7,718,471 · App. 12/269,798 · Granted May 18, 2010

Method and apparatus for stacked die package with insulated wire bonds

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Quick Facts
Patent No.
US 7,718,471
App. No.
12/269,798
Granted
May 18, 2010
Kind
B1
Abstract

A semiconductor package has a substrate with a plurality of contact pads. A first semiconductor die is mounted to the substrate. First wire bonds are formed between each of the center-row contact pads of the first semiconductor die and the substrate contact pads. The first wire bonds include an electrically insulative coating formed over the shaft that covers a portion of a surface of a bumped end of the first wire bonds. An epoxy material is deposited over the first semiconductor die. A second semiconductor die is mounted to the epoxy material. Second wire bonds are formed between each of the center-row contact pads of the second semiconductor die and the substrate contact pads. The second wire bonds include an electrically insulative coating formed over the shaft of the second wire bonds that covers a portion of a surface of a bumped end of the second wire bonds.

Claims (37)

1. A method of making a semiconductor package, comprising:

providing a substrate having a plurality of contact pads formed over a first surface of the substrate;

mounting a first semiconductor die to the substrate, the first semiconductor die having center-row contact pads;

forming first wire bonds between each of the center-row contact pads of the first semiconductor die and the plurality of contact pads formed over the first surface of the substrate, the first wire bonds including an electrically insulative coating formed over the shaft of the first wire bonds, and the electrically insulative coating covering a portion of a surface of a bumped end of the first wire bonds;

depositing an epoxy material over the first semiconductor die and around a portion of the first wire bonds;

mounting a second semiconductor die to the epoxy material, the second semiconductor die having center-row contact pads;

forming second wire bonds between each of the center-row contact pads of the second semiconductor die and the plurality of contact pads formed over the first surface of the substrate, the second wire bonds including an electrically insulative coating formed over the shaft of the second wire bonds, and the electrically insulative coating covering a portion of a surface of a bumped end of the second wire bonds; and

forming an interconnect structure on a second surface of the substrate opposite the first surface.

2. The method of claim 1 , wherein the epoxy material includes liquid dispensed spacerless epoxy or dry film epoxy.

3. The method of claim 1 , wherein the interconnect structure includes a plurality of solder bumps.

4. The method of claim 1 , wherein the first and second wire bonds include an insulated gold (Au) material.

5. The method of claim 1 , including applying a force to a top surface of the second semiconductor die to decrease a distance between the first and second semiconductor dies.

6. The method of claim 1 , wherein the substrate includes an epoxy-based laminate, or Bismaleimide-Triazine (BT) laminate material.

7. The method of claim 1 , wherein a bottom surface of the second semiconductor die contacts one of the first wire bonds.

8. A method of making a semiconductor package, comprising:

providing a substrate having a plurality of contact pads formed over a first surface of the substrate;

mounting a first semiconductor die to the substrate, the first semiconductor die having center-row contact pads;

forming first wire bonds between each of the center-row contact pads of the first semiconductor die and the plurality of contact pads formed over the first surface of the substrate, the first wire bonds including an electrically insulative coating formed over the shaft of the first wire bonds, and the electrically insulative coating covering a portion of a surface of a bumped end of the first wire bonds;

depositing an insulating material over the first semiconductor die and around a portion of the first wire bonds;

mounting a second semiconductor die to the epoxy material, the second semiconductor die having contact pads; and

forming second wire bonds between each of the contact pads of the second semiconductor die and the plurality of contact pads formed over the first surface of the substrate.

9. The method of claim 8 , wherein the insulating material includes liquid dispensed spacerless epoxy or dry film epoxy.

10. The method of claim 8 , including forming an interconnect structure over a second surface of the substrate.

11. The method of claim 8 , wherein the first and second wire bonds include an insulated gold (Au) material.

12. The method of claim 8 , including applying a force to a top surface of the second semiconductor die to decrease a distance between the first and second semiconductor dies.

13. The method of claim 8 , wherein the substrate includes an epoxy-based laminate, or Bismaleimide-Triazine (BT) laminate material.

14. A method of making a semiconductor package, comprising:

providing a substrate having a plurality of contact pads formed over a first surface of the substrate;

mounting a first semiconductor die to the substrate, the first semiconductor die having center-row contact pads;

forming first wire bonds between each of the center-row contact pads of the first semiconductor die and the plurality of contact pads formed over the first surface of the substrate, the first wire bonds including an electrically insulative coating formed over the shaft of the first wire bonds;

depositing an insulating material over the first semiconductor die and around a portion of the first wire bonds; and

mounting a second semiconductor die to the epoxy material, the second semiconductor die having contact pads.

15. The method of claim 14 , including forming second wire bonds between each of the contact pads of the second semiconductor die and the plurality of contact pads formed over the first surface of the substrate.

16. The method of claim 14 , wherein the insulating material includes liquid dispensed spacerless epoxy or dry film epoxy.

17. The method of claim 14 , including applying a force to a top surface of the second semiconductor die to decrease a distance between the first and second semiconductor dies.

18. The method of claim 14 , wherein the substrate includes an epoxy-based laminate, or Bismaleimide-Triazine (BT) laminate material.

19. The method of claim 14 , including forming an interconnect structure over a second surface of the substrate.

Assignments (11)
NOTICE OF SUCCESSOR AGENT AND ASSIGNMENT OF SECURITY INTEREST IN REEL/FRAME 038589/0305 Recorded Nov 7, 2025
From: BANK OF AMERICA, N.A., AS PREDECESSOR AGENT
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS SUCCESSOR AGENT
Reel/Frame 073506/0385 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded May 3, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI LLC - RF INTEGRATED SOLUTIONS; MICROSEMI CORPORATION; MICROSEMI CORP. - MEMORY AND STORAGE SOLUTIONS
Reel/Frame 038599/0667 →
SECURITY AGREEMENT Recorded May 2, 2016
From: MERCURY SYSTEMS, INC.; MERCURY DEFENSE SYSTEMS, INC.; MICROSEMI CORP.-SECURITY SOLUTIONS; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 038589/0305 →
REGISTERED IP ASSIGNMENT AGREEMENT Recorded Apr 25, 2016
From: MICROSEMI CORPORATION
To: MICROSEMI CORP. - MEMORY AND STORAGE SOLUTIONS
Reel/Frame 038521/0378 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2011
From: WHITE ELECTRONIC DESIGNS CORP.; ACTEL CORPORATION; MICROSEMI CORPORATION
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 025783/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2010
From: WHITE ELECTRONIC DESIGNS CORPORATION
To: MICROSEMI CORPORATION
Reel/Frame 024710/0987 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2008
From: ZACCARDI, JAMES
To: WHITE ELECTRONIC DESIGNS CORPORATION
Reel/Frame 021834/0070 →