Trench shielding structure for semiconductor device and method
A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.
1. A semiconductor device structure comprising:
a region of semiconductor material having a first major surface;
a first trench structure formed in an active area of the semiconductor device, wherein the first trench structure includes a first trench, a first control electrode, and a first shield electrode;
a control pad formed overlying the first major surface and coupled to the first control electrode;
a second trench structure formed in the region of semiconductor material, wherein the second trench structure includes a second trench, an insulator layer and a second shield electrode, and wherein the second shield electrode and the first shield electrode are coupled together, and wherein the control pad overlaps at least a portion of the second shield electrode;
a dielectric layer formed between the control pad and the second trench structure, wherein the dielectric layer isolates the control pad from the second shield electrode; and
a first control runner connecting the control pad to the first control electrode, wherein the first control runner overlaps a least a portion of the second shield electrode.
2. The structure of claim 1 , wherein the second trench structure includes a plurality of trenches, wherein the plurality of trenches has a trench spacing less than about 0.3 microns.
3. The structure of claim 1 , wherein the structure is absent any intervening conductive layers between the second trench structure and the control pad.
4. The structure of claim 1 , wherein the second trench structure is formed absent a control electrode.
5. The structure of claim 1 , wherein the second trench extends from a first side of the control pad to another side of the control pad opposite to the first side.
6. The structure of claim 1 , wherein the first and second shield electrodes are coupled together with a shield electrode runner overlying the first major surface.
7. The structure of claim 6 , wherein the second shield electrode does not overlap the first major surface, and wherein a conductive structure connects the shield electrode runner to the second shield electrode.
8. The structure of claim 1 , wherein the second trench structure includes a plurality of trenches each having a depth, wherein the plurality of trenches are spaced a distance less than about one-half the depth.
9. The structure of claim 1 , wherein the control pad makes direct contact to the first control electrode underneath a portion of the control pad.
10. A semiconductor device structure comprising:
a region of semiconductor material having a major surface and first and second opposing edges;
a first trench formed in the region of semiconductor material extending in a direction from the first edge to the second edge;
a first shield electrode formed in the first trench;
a first control electrode formed in the first trench;
a second trench formed in the region of semiconductor material;
an insulator layer formed in the second trench;
a second shield electrode formed in the second trench overlying the insulator layer;
a control pad overlying at least a portion of the second trench, wherein the control pad is coupled to the first control electrode;
a dielectric layer overlying the second trench isolating the second shield electrode from the control pad; and
a first shield electrode runner formed overlying the major surface, wherein the first shield electrode runner is coupled to the second shield electrode, and wherein the first shield electrode is coupled to the second shield electrode adjacent the first edge, and wherein the structure further comprises a second shield electrode runner coupled to the second shield electrode adjacent the second edge.
11. The structure of claim 10 further comprising:
a control electrode runner connecting the control pad to the first control electrode;
a third trench formed in the region of semiconductor material below at least a portion of the control electrode runner; and
a third shield electrode formed in the third trench, wherein the second and third trenches are formed absent control electrodes.
12. The structure of claim 11 , wherein the dielectric layer overlies the third trench and isolates the control pad from the third shield electrode.
13. A semiconductor device structure comprising:
a region of semiconductor material having a first major surface;
a first trench structure formed in an active area of the semiconductor device, wherein the first trench structure includes a first trench, a first control electrode, and a first shield electrode;
a control pad formed overlying the first major surface and coupled to the first control electrode;
a second trench structure formed in the region of semiconductor material underlying at least a portion of the control pad, wherein the second trench structure includes a second trench, an insulator layer and a second shield electrode, and wherein the second shield electrode and the first shield electrode are coupled together with a first shield electrode runner adjacent a first edge, and wherein the second trench structure is formed absent a control electrode;
a dielectric layer formed between the control pad and the second trench structure, wherein the dielectric layer isolates the control pad from the second shield electrode; and
a second shield electrode runner coupled to the second shield electrode adjacent a second edge.
14. The structure of claim 13 , wherein the second trench structure includes a plurality of trenches each having a depth, wherein the plurality of trenches are spaced a distance less than about one-half the depth.
15. The structure of claim 13 further comprising a first control runner connecting the control pad to the first control electrode, wherein the second trench structure is further formed underlying at least a portion of the first control runner.
16. The structure of claim 13 , wherein the structure is formed absent any conductive layers overlying the major surface between the control pad and the second trench structure.
17. A method of forming a semiconductor device comprising the steps of:
providing a region of semiconductor material having a major surface and first and second opposing edges;
forming a first trench in the region of semiconductor material extending in a direction from the first edge to the second edge;
forming a first shield electrode in the first trench;
forming a first control electrode in the first trench;
forming a second trench in the region of semiconductor material;
forming an insulator layer in the second trench;
forming a second shield electrode in the second trench overlying the insulator layer;
forming a dielectric layer overlying the second shield electrode;
forming a control pad overlying and overlapping at least a portion of the second shield electrode, wherein the control pad is coupled to the first control electrode, and wherein the dielectric layer isolates the control pad from the second shield electrode; and
forming a first control runner connecting the control pad to the first control electrode, wherein the first control runner overlaps a least a portion of the second shield electrode.