IP Library Granted Patent US 8,106,502
Granted Patent B2
US 8,106,502 · App. 12/272,751 · Granted Jan 31, 2012

Integrated circuit packaging system with plated pad and method of manufacture thereof

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,106,502
App. No.
12/272,751
Granted
Jan 31, 2012
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

Claims (64)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming an external interconnect;

forming a first planar terminal, made only of plated metal layers, adjacent to the external interconnect and non-planar to a portion of the external interconnect;

mounting a first integrated circuit over the first planar terminal;

connecting the first integrated circuit with the external interconnect; and

forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

2. The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation along a perimeter of the first planar terminal is planar to the first planar terminal.

3. The method as claimed in claim 1 wherein:

forming the first planar terminal includes forming a second planar terminal; and

further comprising:

connecting the first integrated circuit and the second planar terminal.

4. The method as claimed in claim 1 further comprising:

mounting a second integrated circuit over the first integrated circuit; and

connecting the second integrated circuit and the first integrated circuit.

5. The method as claimed in claim 1 wherein:

forming the first planar terminal includes forming a second planar terminal; and

further comprising:

connecting the external interconnect and the second planar terminal.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming a lead;

plating a first planar terminal and a second planar terminal adjacent and planar to each other, and both adjacent to the lead and non-planar to a portion the lead, the first planar terminal and the second planar terminal made only of plated metal layers;

mounting a first integrated circuit over the first planar terminal;

connecting the first integrated circuit with the lead; and

forming an encapsulation over the first planar terminal covering the first integrated circuit and with the lead extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation along a perimeter of the first planar terminal exposing the first planar terminal.

7. The method as claimed in claim 6 wherein forming the encapsulation includes forming the encapsulation having a cavity with the first planar terminal and the second planar terminal exposed within the cavity.

8. The method as claimed in claim 6 further comprising mounting a device to the second planar terminal.

9. The method as claimed in claim 6 wherein:

forming the encapsulation includes forming the encapsulation having a cavity with the second planar terminal exposed within the cavity; and

further comprising:

mounting a device in the cavity and over the second planar terminal.

10. The method as claimed in claim 6 wherein:

forming the encapsulation includes forming the encapsulation having a cavity with the second planar terminal exposed within the cavity; and

further comprising:

attaching an external connector to the second planar terminal.

11. An integrated circuit packaging system comprising:

an external interconnect;

a first planar terminal, made only of plated metal layers, adjacent to the external interconnect and non-planar to a portion of the external interconnect;

a first integrated circuit over the first planar terminal and connected with the external interconnect; and

an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

12. The system as claimed in claim 11 wherein the encapsulation includes the encapsulation along a perimeter of the first planar terminal is planar to the first planar terminal.

13. The system as claimed in claim 11 further comprising:

a second planar terminal adjacent to and planar with the first planar terminal; and

wherein:

the first integrated circuit is connected to the second planar terminal.

14. The system as claimed in claim 11 further comprising a second integrated circuit over and connected to the first integrated circuit.

15. The system as claimed in claim 11 further comprising:

a second planar terminal adjacent to and planar with the first planar terminal; and

wherein:

the external interconnect is connected to the second planar terminal.

16. The system as claimed in claim 11 wherein:

the external interconnect is a lead;

the encapsulation along a perimeter of the first planar terminal is planar to the first planar terminal; and

further comprising:

a second planar terminal adjacent and planar to the first planar terminal.

17. The system as claimed in claim 16 wherein the encapsulation includes the encapsulation having a cavity with the first planar terminal and the second planar terminal exposed within the cavity.

18. The system as claimed in claim 16 further comprising a device mounted to the second planar terminal.

19. The system as claimed in claim 16 wherein:

the encapsulation includes the encapsulation having a cavity with the second planar terminal exposed within the cavity; and

further comprising:

a device in the cavity and over the second planar terminal.

20. The system as claimed in claim 16 wherein:

the encapsulation includes the encapsulation having a cavity with the second planar terminal exposed within the cavity; and

further comprising:

an external connector attached to the second planar terminal.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2008
From: BATHAN, HENRY DESCALZO; CAMACHO, ZIGMUND RAMIREZ; PISIGAN, JAIRUS LEGASPI; TAY, LIONEL CHIEN HUI
To: STATS CHIPPAC LTD.
Reel/Frame 021897/0266 →
Continuity (1)
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