Semiconductor devices and methods of manufacture thereof
View Patent ↗A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the gate electrode material(s) can be deposited conformally. Provision of at least one upstanding structure (or “dummy fin”) ( 40 ) on each side of the fin ( 4 ) serves to locally increase the thickness of the gate electrode material layer ( 70 ). In particular, as the shortest distance between each upstanding structure ( 40 ) and the respective side of the fin ( 4 ) is arranged in accordance with the invention to be less than twice the thickness of the conformal layer, the thickness of the gate electrode material layer ( 70 ) all the way across this distance between each upstanding structure ( 40 ) and the fin ( 4 ) is increased relative to that over planar regions of the substrate ( 2 ). Thus, following an anisotropic etch to remove gate electrode material ( 70 ) overlying the fin ( 4 ), some material nevertheless remains between the upstanding structures and the fin. Thus, an enlarged area of gate electrode material is formed for use as a gate contact pad.
1. A method of manufacturing a semiconductor device, including the steps of:
(a) providing a substrate having an insulating top surface;
(b) forming a fin of semiconductor material on the top surface of the substrate, the fin having first and second opposite sides;
(c) forming at least one upstanding structure on each side of the fin laterally spaced from the respective side of the fin;
(d) depositing a conformal layer of gate electrode material;
(e) patterning the layer of gate electrode material; and
(f) anisotropically etching away gate electrode material until the gate electrode material adjacent the first side of the fin is separated from the gate electrode material on the second side of the fin, the shortest distance between each upstanding structure and the respective side of the fin being less than twice the thickness of the conformal layer deposited in step (d).
2. A method of claim 1 wherein step (f) is carried out before step (e).
3. A method of claim 1 wherein the semiconductor device includes at least one additional fin of semiconductor material and at least one of the upstanding structures is provided by the at least one additional fin.
4. A method of claim 1 , wherein at least one of the upstanding structures is an island of inactive material.
5. A method of claim 4 wherein the island of material comprises semiconductor material formed from the same layer as the fin.
6. A method of claim 1 , wherein the conformal layer of gate electrode material comprises a layer of polycrystalline semiconductor material over a metallic layer.
7. A method of claim 1 , wherein the gate electrode material of the finished device comprises at least one of polycrystalline semiconductor material, a metal, titanium nitride, tantalum nitride and fully silicided polycrystalline semiconductor material.
8. A method of claim 1 , wherein at least one additional semiconductor device having a fin is formed simultaneously on the same substrate, and gate electrode material over the fin of the at least one additional device is masked during step (f) so that the gate electrode material is continuous from one side of the fin to the other in the finished additional device.
9. A method of claim 1 , wherein at least two upstanding structures are provided laterally spaced from each side of the fin.
10. A method of claim 1 , wherein at least one upstanding structure is L-shaped in plan view.