Three terminal nonvolatile memory device with vertical gated diode

1. A three terminal nonvolatile memory cell, comprising:

a diode;

a control gate; and

a charge storage medium located between the diode and the control gate;

wherein the diode comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type;

wherein the diode comprises a vertical diode, and the second semiconductor region is located above the first semiconductor region;

wherein a first electrode which contacts the first semiconductor region is located below the first semiconductor region, and a second electrode which contacts the second semiconductor region is located above the second semiconductor region.

2. The cell of claim 1 , wherein the first semiconductor region has a first conductivity type dopant density between 1×10 19 and 1×10 21 cm −3 , and the second semiconductor region has a second conductivity type dopant density between 1×10 19 and 1×10 21 cm −3 .

3. The cell of claim 2 , further comprising a third semiconductor region of the first conductivity type located between the first and the second semiconductor regions.

4. The cell of claim 3 , wherein the third semiconductor region has a first conductivity type dopant density between 1×10 16 and 1×10 18 cm −3 .

5. The cell of claim 1 , wherein the charge storage medium contacts the second semiconductor region and the control gate contacts the charge storage medium.

6. The cell of claim 5 , wherein the control gate is located above the first electrode and below the second electrode.

7. The cell of claim 5 , wherein the charge storage medium comprises a dielectric isolated floating gate.

8. The cell of claim 5 , wherein the charge storage medium comprises a dielectric stack.

9. The cell of claim 8 , wherein the dielectric stack comprises a nitride layer located between two oxide layers.

10. The cell of claim 1 , further comprising a second nonvolatile memory cell comprising a second diode and a second charge storage medium.

11. The cell of claim 10 , wherein the control gate is shared between the nonvolatile memory cell and the second nonvolatile memory cell.

12. The cell of claim 11 , wherein the control gate contacts the charge storage medium and the second charge storage medium.

13. The cell of claim 1 , wherein the cell comprises a portion of a monolithic three dimensional array of nonvolatile memory cells.

14. The cell of claim 13 , wherein cell size per bit is about (2f 2 )/N, where f is a minimum feature size and N is a number of device layers in a third dimension, and where N≧1.

15. An array of nonvolatile memory cells, comprising:

a first nonvolatile memory cell comprising a first vertical diode located over a substrate and a first charge storage medium located adjacent to a side of the first vertical diode;

a second nonvolatile memory cell comprising a second vertical diode located over the substrate and a second charge storage medium located adjacent to a side of the second vertical diode;

a control gate which is located between and contacts the first charge storage medium and the second charge storage medium;

wherein:

the first nonvolatile memory cell is located adjacent to the second nonvolatile memory cell; and

the control gate is shared between the first and the second nonvolatile memory cells.

16. The array of claim 15 , wherein:

the first vertical diode comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located above the first semiconductor region;

the second vertical diode comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type located above the first semiconductor region; and

the first and the second charge storage medium each comprise a dielectric isolated floating gate or a dielectric stack.

17. The array of claim 16 , further comprising:

a first electrode which contacts the first semiconductor region of the first vertical diode and which is located below the first semiconductor region of the first vertical diode; and

a second electrode which contacts the second semiconductor region of the first vertical diode and which is located above the second semiconductor region of the first vertical diode;

a third electrode which contacts the first semiconductor region of the second vertical diode and which is located below the first semiconductor region of the second vertical diode; and

a fourth electrode which contacts the second semiconductor region of the second vertical diode and which is located above the second semiconductor region of the second vertical diode.

18. A three terminal nonvolatile memory cell, comprising:

a first electrode;

a second electrode;

a semiconductor pillar located between the first and second electrodes, such that the semiconductor pillar is in contact with the first and the second electrodes;

a control gate; and

a charge storage medium located between the semiconductor pillar and the control gate, wherein the charge storage medium comprises:

a tunneling dielectric in contact with the semiconductor pillar;

a floating gate in contact with the tunneling dielectric; and

a control gate dielectric in contact with the floating gate;

wherein the pillar consists essentially of a diode, and the diode consists essentially of:

a first semiconductor region of a first conductivity type in contact with the first electrode and a second semiconductor of a second conductivity type in contact with the second electrode; or

a first semiconductor region of a first conductivity type in contact with the first electrode, a second semiconductor of a second conductivity type in contact with the second electrode, and a third semiconductor region of the first conductivity type located between the first semiconductor region and the second semiconductor region.