Insulated gate e-mode transistors
Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.
1. A III-nitride HEMT device, comprising:
a gate electrode;
a source electrode and a drain electrode;
a series of III-nitride layers forming an N-face stack with an uppermost layer with which the source and drain electrodes form ohmic contacts; and
a channel depleting portion between the gate electrode and the uppermost layer of the N-face stack, wherein the channel depleting portion does not extend all the way to the source electrode.
2. The device of claim 1 , wherein the uppermost layer is a channel layer in which a 2DEG is formed in an access region of the device.
3. The device of claim 2 , wherein a gate region of the channel layer does not contain a 2DEG in the absence of a voltage applied to the gate electrode, and the device is an enhancement mode device.
4. The device of claim 1 , wherein the uppermost layer includes a recess in a gate region and the channel depleting portion is in the recess.
5. The device of claim 1 , further comprising a channel charge enhancing layer on the uppermost layer, contacting the channel depleting portion and extending toward the source electrode and the drain electrode.
6. The device of claim 5 , further comprising a field plate extending toward the drain electrode.
7. The device of claim 6 , wherein the channel depleting portion extends partially toward the drain electrode.
8. The device of claim 5 , wherein the channel charge enhancing layer comprises SiN.
9. The device of claim 1 , further comprising a p-type III-nitride region between the channel depleting portion and the uppermost layer of the N-face stack.
10. The device of claim 9 , wherein the p-type III-nitride region extends from the source electrode to the drain electrode, and the device further includes an additional GaN layer in an access region of the device adjacent to the p-type III-nitride on a side opposite the uppermost layer.
11. The device of claim 9 , wherein the p-type III-nitride region includes Al z GaN, wherein 0.05≦z≦0.35.
12. The device of claim 1 , wherein the channel depleting portion includes a high-K dielectric.
13. The device of claim 1 , wherein the channel depleting portion is formed of AlSiN, Ta 2 O 5 , HfO 2 or ZrO 2 .
14. A III-nitride HEMT device, comprising:
a gate electrode;
a source electrode and a drain electrode;
a series of III-nitride layers forming a Ga-face stack with an uppermost layer, and a channel layer with which the source and drain electrodes form ohmic contacts;
a dielectric layer on the uppermost layer and over an access region of the device;
a channel depleting portion between the gate electrode and the uppermost layer of the Ga-face stack, wherein the channel depleting portion does not extend all the way to the source electrode; and
a charge enhancing III-nitride layer between the dielectric layer and the uppermost layer and surrounding the channel depleting portion.
15. The device of claim 14 , wherein a 2DEG is formed in an access region of the channel layer of the device.
16. The device of claim 15 , wherein a gate region of the channel layer does not contain a 2DEG in an absence of a voltage applied to the gate electrode, and the device is an enhancement mode device.
17. The device of claim 14 , wherein the channel depleting portion includes a high-K dielectric.
18. The device of claim 14 , wherein the channel depleting portion is formed of AlSiN, Ta 2 O 5 , HfO 2 or ZrO 2 .
19. The device of claim 14 , wherein the channel depleting portion extends part way toward the drain electrode, but does not contact the drain electrode.
20. The device of claim 19 , further comprising a field plate extending towards the drain electrode.
21. The device of claim 14 , further comprising an interlayer of AlN between the uppermost layer and the channel layer.
22. The device of claim 14 , further comprising a GaN layer between the charge enhancing III-nitride layer and the uppermost layer of the Ga-face stack.
23. The device of claim 21 , wherein the uppermost layer is a p-type layer.
24. The device of claim 14 , further comprising a field plate.
25. A III-nitride HEMT device, comprising:
a gate electrode;
a source electrode and a drain electrode;
a series of III-nitride layers forming a Ga-face stack with an uppermost layer and a channel layer with which the source and drain electrodes form ohmic contacts;
a channel depleting portion between the gate electrode and the uppermost layer of the Ga-face stack, wherein the channel depleting portion does not extend all the way to the source electrode;
a charge enhancing III-nitride layer over the uppermost layer of the Ga-face stack and surrounding the channel depleting portion; and
a GaN layer between the charge enhancing III-nitride layer and the uppermost layer of the Ga-face stack.
26. The device of claim 25 , wherein a gate region of the channel layer does not contain a 2DEG in an absence of a voltage applied to the gate electrode, and the device is an enhancement mode device.
27. A normally off III-nitride HEMT device, comprising:
an upper gate electrode;
a source electrode and a drain electrode;
a series of III-nitride layers forming a Ga-face stack with an uppermost layer and a channel layer with which the source and drain electrodes form ohmic contacts, wherein the series of III-nitride layers includes a p-type III-nitride capping layer adjacent to a III-nitride type covering layer on an N-face of the series and an aperture in the covering layer exposes a portion of the p-type III-nitride capping layer; and
a channel depleting portion either between the upper gate electrode and the uppermost layer of the Ga-face stack, wherein the channel depleting portion does not extend all the way to the source electrode.
28. The device of claim 27 , further comprising a p-type III-nitride type cap portion between the uppermost layer and the upper gate electrode.
29. The device of claim 27 , further comprising a lower gate electrode in or adjacent to the aperture in the covering layer.
30. The device of claim 27 , wherein a gate region of the uppermost layer is treated with fluorine.
31. A normally off III-nitride HEMT device, comprising:
an upper gate electrode;
a source electrode and a drain electrode; and
a series of III-nitride layers forming a Ga-face stack with an uppermost layer and a channel layer with which the source and drain electrodes form ohmic contacts, wherein the series of III-nitride layers includes a lower III-nitride layer adjacent to a III-nitride type covering layer on an N-face of the series and an aperture in the covering layer exposes a portion of the lower III-nitride layer; and
a channel depleting portion either between the upper gate electrode and the uppermost layer of the Ga-face stack, wherein the channel depleting portion does not extend all the way to the source electrode;
wherein at least one of the uppermost layer in the gate region or the exposed portion of the lower III-nitride layer is treated with fluorine.
32. A normally off III-nitride HEMT device, comprising:
a gate electrode;
a source electrode and a drain electrode;
a series of semi-polar or nonpolar III-nitride layers with an uppermost layer, and a channel layer with which the source and drain electrodes form ohmic contacts; and
a channel depleting portion between the gate electrode and the uppermost layer of the N-face stack, wherein the channel depleting portion does not extend all the way to the source electrode.
33. The device of claim 32 , wherein the uppermost layer is doped n-type.