IP Library Granted Patent US 7,994,629
Granted Patent B2
US 7,994,629 · App. 12/329,467 · Granted Aug 9, 2011

Leadless integrated circuit packaging system and method of manufacture thereof

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Quick Facts
Patent No.
US 7,994,629
App. No.
12/329,467
Granted
Aug 9, 2011
Kind
B2
Abstract

A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.

Claims (42)

1. A method of manufacture of a leadless integrated circuit packaging system comprising:

providing a substrate;

patterning a die attach pad on the substrate;

forming a tiered plated pad array including forming multiple heights of plated pads around the die attach pad, plated layers of a shortest height plated pad of the plated pads being a subset to the plated layers of the rest of the plated pads:

mounting an integrated circuit die on the die attach pad;

coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array;

forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and

exposing a contact pad layer by removing the substrate.

2. The method as claimed in claim 1 wherein forming the tiered plated pad array includes plating a one tier plated pad, a two tier plated pad, a three tier plated pad, or a combination thereof.

3. The method as claimed in claim 1 wherein coupling the electrical interconnect to the tiered plated pad array includes coupling a connection cap layer to the electrical interconnect.

4. The method as claimed in claim 1 wherein forming the tiered plated pad array includes forming a one tiered plated pad adjacent to the die attach pad.

5. The method as claimed in claim 1 wherein exposing the contact pad layer includes revealing a package contact surrounded by the molded package body.

6. A method of manufacture of a leadless integrated circuit packaging system comprising:

providing a substrate including having a planar surface on the substrate;

patterning a die attach pad on the substrate including applying a first mask layer on the planar surface;

forming a tiered plated pad array including forming multiple heights of plated pads around the die attach pad, plated layers of a shortest height plated pad of the plated pads being a subset to the plated layers of the rest of the plated pads;

mounting an integrated circuit die on the die attach pad including applying an adhesive between the die attach pad and the integrated circuit die;

coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array;

forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and

exposing a contact pad layer by removing the substrate including providing a package contact in the molded package body.

7. The method as claimed in claim 6 wherein forming the tiered plated pad array includes plating a one tier plated pad, a two tier plated pad, a three tier plated pad, or a combination thereof including plating a spacer metal between the contact pad layer and a connection cap layer.

8. The method as claimed in claim 6 wherein coupling the electrical interconnect to the tiered plated pad array includes coupling a connection cap layer to the electrical interconnect including coupling a bond pad on the integrated circuit die.

9. The method as claimed in claim 6 wherein forming the tiered plated pad array includes forming a one tier plated pad adjacent to the die attach pad including forming a two tier plated pad between the one tier plated pad and a three tier plated pad.

10. The method as claimed in claim 6 wherein exposing the contact pad layer includes revealing a package contact surrounded by the molded package body including revealing a gold layer.

11. A leadless integrated circuit packaging system comprising:

a die attach pad;

a tiered plated pad array includes multiple heights of plated pads around the die attach pad, plated layers of a shortest height plated ad of the plated pads being a subset to the plated layers of the rest of the plated pads;

an integrated circuit die mounted on the die attach pad;

an electrical interconnect coupled to the tiered plated pad array and the integrated circuit die;

a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and

a contact pad layer on a package bottom of the molded package body.

12. The system as claimed in claim 11 wherein the tiered plated pad array includes a one tier plated pad, a two tier plated pad, a three tier plated pad, or a combination thereof.

13. The system as claimed in claim 11 wherein the electrical interconnect coupled to the tiered plated pad array includes a connection cap layer coupled to the electrical interconnect.

14. The system as claimed in claim 11 wherein the tiered plated pad array includes a one tier plated pad adjacent to the die attach pad.

15. The system as claimed in claim 11 wherein the contact pad layer on the package bottom includes a package contact surrounded by the molded package body.

16. The system as claimed in claim 11 further comprising:

an adhesive between the die attach pad and the integrated circuit die; and

a package contact in the molded package body.

17. The system as claimed in claim 16 wherein the tiered plated pad array includes a one tier plated pad, a two tier plated pad, a three tier plated pad, or a combination thereof including a spacer metal between the contact pad layer and a connection cap layer.

18. The system as claimed in claim 16 wherein the electrical interconnect coupled to the tiered plated pad array includes a connection cap layer coupled to the electrical interconnect and a bond pad on the integrated circuit die.

19. The system as claimed in claim 16 wherein the tiered plated pad array includes a one tier plated pad adjacent to the die attach pad including a two tier plated pad between the one tier plated pad and a three tier plated pad.

20. The system as claimed in claim 16 wherein the contact pad layer includes the package contact surrounded by the molded package body includes a gold layer.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0301. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064913/0352 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0301 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2008
From: CAMACHO, ZIGMUND RAMIREZ
To: STATS CHIPPAC LTD.
Reel/Frame 021989/0581 →