Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods

1. A method for fabricating a semiconductor device, the method comprising the steps of:

forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate;

forming first sidewall spacers about sidewalls of the gate stack, wherein, after the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed;

anisoptropically etching the exposed portion of the first gate stack-forming layer using the gate stack and the first sidewall spacers as an etch mask; and

forming second sidewall spacers adjacent the first sidewall spacers after the step of anisotropically etching.

2. The method of claim 1 , wherein the step of forming a gate stack comprising a first gate stack-forming layer comprises forming a gate stack comprising a gate insulator material.

3. The method of claim 2 , wherein the step of forming a gate stack comprising a gate insulator material comprises forming a gate stack comprising a high dielectric constant material.

4. The method of claim 3 , wherein the step of forming the gate stack comprising a high dielectric constant material comprises forming the gate stack using a material selected from the group consisting of hafnium silicate, hafnium dioxide, hafnium silicon oxynitride, zinc dioxide, and zirconium oxide.

5. The method of claim 1 , wherein the step of forming a gate stack comprising a first gate stack-forming layer comprises forming a gate stack comprising a metal gate-forming material.

6. The method of claim 5 , wherein the step of forming the gate stack comprising a metal gate-forming material comprises forming a gate stack comprising a material selected from the group consisting of lanthanum, lanthanum alloys, aluminum, aluminum alloys, magnesium, magnesium alloys, titanium-based materials, and tantalum-based materials.

7. The method of claim 1 , wherein the step of forming first sidewall spacers comprises forming the first sidewall spacers so that each has a thickness in the range of about 2 to about 9 nm.

8. The method of claim 1 , wherein the step of forming a gate stack comprising a first gate stack-forming layer comprises forming a gate stack comprising a high dielectric constant material and an overlying metal gate-forming material.

9. The method of claim 1 , wherein the step of forming a gate stack comprising a first gate stack-forming layer comprises the steps of:

forming the first gate stack-forming layer overlying the semiconductor substrate;

forming a second gate stack-forming layer overlying the first gate stack-forming layer, wherein the second gate stack-forming layer has a composition different from the first gate stack-forming layer; and

etching the first gate stack-forming layer and the second gate stack-forming layer to form the gate stack.

10. The method of claim 9 , wherein the step of forming a second gate stack-forming layer comprises depositing polycrystalline or amorphous silicon overlying the first gate stack-forming layer.

11. A method for fabricating a semiconductor device, the method comprising the steps of:

forming a first gate stack-forming layer overlying a semiconductor substrate;

forming a second gate stack-forming layer overlying the first gate stack-forming layer;

etching the first gate stack-forming layer and the second gate stack-forming layer to form a gate stack, wherein, after the step of etching, a first portion of the first gate stack-forming layer underlies the second gate stack-forming layer and a second portion of the first gate stack-forming layer has an exposed surface;

forming a first sidewall spacer about sidewalls of the second gate stack-forming layer;

anisoptropically etching the second portion of the first gate stack-forming layer using the gate stack and the first sidewall spacer as an etch mask; and

forming a second sidewall spacer adjacent the first sidewall spacer and the exposed surface of the second portion of the first gate stack-forming layer.

12. The method of claim 11 , wherein the semiconductor substrate comprises a shallow trench isolation region having a divot and wherein the step of forming a first gate stack-forming layer comprises forming a portion of the first gate stack-forming layer in the divot.

13. The method of claim 11 , wherein the step of forming a first gate stack-forming layer comprises forming a first gate stack-forming layer having a gate insulator material.

14. The method of claim 13 , wherein the step of forming a first gate stack-forming layer having a gate insulator material comprises forming the first gate stack-forming layer using a high dielectric constant material.

15. The method of claim 11 , wherein the step of forming a first gate stack-forming layer comprises forming a first gate stack-forming layer having a metal gate-forming material.

16. The method of claim 15 , wherein the step of forming a first gate stack-forming layer having a metal gate-forming material comprises forming the first gate stack-forming layer using a material selected from the group consisting of lanthanum, lanthanum alloys, aluminum, aluminum alloys, magnesium, magnesium alloys, titanium-based materials, and tantalum-based materials.

17. The method of claim 11 , wherein the step of forming a first sidewall spacer comprises forming the first sidewall spacer so that it has a thickness in the range of about 2 to about 9 nm.

18. The method of claim 11 , wherein the step of forming a second sidewall spacer comprises forming the second sidewall spacer so that it has a thickness in the range of about 2 to about 9 nm.

19. The method of claim 11 , wherein the step of forming a second gate stack-forming layer comprises forming polycrystalline or amorphous silicon overlying the first gate stack-forming layer.