IP Library Granted Patent US 7,919,850
Granted Patent B2
US 7,919,850 · App. 12/331,416 · Granted Apr 5, 2011

Integrated circuit packaging system with exposed terminal interconnects and method of manufacturing thereof

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 7,919,850
App. No.
12/331,416
Granted
Apr 5, 2011
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.

Claims (61)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a lead;

mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad;

forming an exposed terminal interconnect on the connection pad; and

encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.

2. The method as claimed in claim 1 further comprising:

mounting a first integrated circuit die above the inner package; and

connecting the first integrated circuit die to the lead or the connection pad with an interconnect.

3. The method as claimed in claim 1 wherein:

providing the lead includes providing a base lead-frame;

mounting the base lead-frame on a coverlay tape;

further comprising:

removing the coverlay tape; and

singulating the base lead-frame from the lead.

4. The method as claimed in claim 1 wherein:

partially encapsulating the exposed terminal interconnect includes exposing a level exposed surface, a bulged exposed surface, or a combination thereof.

5. The method as claimed in claim 1 further comprising:

mounting an external integrated circuit package above the encapsulation; and

connecting the external integrated circuit package to the exposed terminal interconnects with a solder bump, a bond wire or a combination thereof.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a lead;

mounting a dual row inner package or a selectively balled inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad;

forming an exposed terminal interconnect on the connection pad; and

encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation to create a first selectively balled integrated circuit packaging system or a first dual row integrated circuit packaging system.

7. The method as claimed in claim 6 wherein:

mounting the dual row inner package includes mounting a dual row inner package having an inner package die-pad, and the connection pad is a first row connection pad or a second row connection pad.

8. The method as claimed in claim 6 wherein:

mounting the selectively balled inner package includes mounting a selectively balled inner package having a substrate, and the connection pad is a wire-bond connection pad or an exposed terminal interconnect connection pads.

9. The method as claimed in claim 6 further comprising:

mounting a second selectively balled integrated circuit packaging system above the first selectively balled integrated circuit packaging system; and

connecting the exposed terminal interconnect or the lead of the first selectively balled integrated circuit packaging system to an exposed terminal interconnect or a lead of the second selectively balled integrated circuit packaging system.

10. The method as claimed in claim 6 wherein:

connecting the dual row inner package or the selectively balled inner package to the lead with an interconnect.

11. An integrated circuit packaging system comprising:

a lead;

an inner package having a connection pad mounted so that the lead is peripheral to the inner package;

an exposed terminal interconnect formed on the connection pad; and

an encapsulation that encapsulates the inner package, and partially encapsulates the exposed terminal interconnect.

12. The system as claimed in claim 11 further comprising:

a first integrated circuit die mounted above the inner package; and

an interconnect that connects the first integrated circuit die to the lead or the connection pad.

13. The system as claimed in claim 11 further comprising:

an external integrated circuit package mounted above the encapsulation;

a base substrate mounted below the lead; and

an exterior encapsulation that encapsulates the external integrated circuit package and the encapsulation.

14. The system as claimed in claim 11 further comprising:

a level exposed surface, a bulged exposed surface, or a combination thereof exposed from the encapsulation on the exposed terminal interconnect.

15. The system as claimed in claim 11 further comprising:

an external integrated circuit package mounted above the encapsulation; and

a solder bump, a bond wire or a combination thereof that connects the external integrated circuit package to the exposed terminal interconnects.

16. The system as claimed in claim 11 wherein:

the inner package is a dual row inner package or a selectively balled inner package that creates a first selectively balled integrated circuit packaging system or a first dual row integrated circuit packaging system.

17. The system as claimed in claim 16 wherein:

the dual row inner package has an inner package die-pad, and the connection pad is a first row connection pad or a second row connection pad.

18. The system as claimed in claim 16 wherein:

the selectively balled inner package has a substrate, and the connection pad is a wire-bond connection pad or an exposed terminal interconnect connection pads.

19. The system as claimed in claim 16 further comprising:

a second selectively balled integrated circuit packaging system mounted above the first selectively balled integrated circuit packaging system; and

a solder interconnect that connects the exposed terminal interconnect or the lead of the first selectively balled integrated circuit packaging system to an exposed terminal interconnect or a lead of the second selectively balled integrated circuit packaging system.

20. The system as claimed in claim 16 wherein:

the dual row inner package or the selectively balled inner package is connected to the lead with an interconnect.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 12, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052924/0007 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2008
From: TRASPORTO, ARNEL SENOSA; TAY, LIONEL CHIEN HUI; CAMACHO, ZIGMUND RAMIREZ; ADVINCULA, ABELARDO JR. HADAP
To: STATS CHIPPAC LTD.
Reel/Frame 022018/0428 →
Continuity (1)
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