Impedance compensated electrostatic discharge circuit for protection of high-speed interfaces and method of using the same
View Patent ↗The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.
1. An apparatus for transmitting a signal and discharging an electrostatic discharge (ESD) event pulse associated with an ESD event to ground to protect a device under protection comprising:
a printed circuit board (“PCB”) having a PCB trace line that transmits the signal, the PCB trace line being formed of first and second line portions that are electrically isolated from one another; and
an electrostatic discharge protection device, separate from the device under protection, and mounted on the printed circuit board to protect the device under protection from the ESD event and for transmitting the signal from the first line portion to the second line portion, the electrostatic discharge protection device including predetermined device parasitics that have an inductance/capacitance ratio that match a PCB trace inductance/capacitance ratio, the electrostatic discharge protection device further including:
an integrated semiconductor, the integrated semiconductor including:
an input pad adapted for electrical coupling to the first line portion of the printed circuit board, that receives the signal and the ESD event pulse associated with the ESD event;
an output pad adapted for electrical coupling to the second line portion of the printed circuit board; and
an electrostatic discharge circuit connected between the input pad and the output pad, the electrostatic discharge circuit providing an electrical path for the signal from the input pad to the output pad and dissipating the ESD event pulse by providing a path to the ground.
2. The apparatus according to claim 1 wherein the inductance/capacitance ratio of the device parasitics is adjusted using first and second bondwires that electrically connect the input pad to the first line portion and the output pad to the second line portion, respectively.
3. The apparatus according to claim 2 , wherein the first and second bondwires are configured to have a parasitic inductance that cancels undesired capacitance that exists from the PCB trace line.
4. The apparatus according to claim 2 wherein a plurality of PCB traces are provided that provide a plurality of channels, and wherein a plurality of bondwires are matched with each other to assist in maintaining the device parasitics that have the inductance/capacitance that matches the PCB trace inductance/capacitance ratio.
5. The apparatus according to claim 1 wherein the inductance/capacitance ratio of the device parasitics is adjusted using the electrostatic discharge circuit.
6. A method of providing impedance compensated electrostatic discharge (ESD) protection for high-speed interfaces comprising:
determining an inductance-to-capacitance characteristic impedance ratio of traces on a printed circuit board (“PCB”), the PCB traces to configured to conduct electric signals across the PCB;
mounting an ESD protection circuit on the PCB connected in series in a PCB trace pathway between a device under protection and the high-speed interface such that a received signal flows through the ESD protection circuit before reaching the device under protection;
adjusting the electrical parasitics of the ESD protection circuit so that its characteristic impedance ratio is compensated to match the characteristic impedance ratio of the PCB traces,
wherein the ESD circuit is operative to permit high frequency components of the received signal to flow through the ESD circuit from the high-speed interface to the device under protection while dissipating any ESD event pulses by providing a path to the ground.
7. The method according to claim 6 wherein the PCB traces include first and second line portions that are electrically isolated from one another, and the ESD protection circuit includes first and second bondwires that electrically connect an input pad of the ESD circuit to the first line portion and an output pad of the ESD circuit to the second line portion, respectively.
8. The method according to claim 7 , wherein the first and second bondwires are configured to have a parasitic inductance that cancels undesired capacitance that exists from the PCB trace line.
9. The method according to claim 7 further comprising matching a plurality of bondwires of a plurality of PCB traces with each other to assist in maintaining the ESD circuit parasitics that have the characteristic impedance ratio equal to the characteristic impedance ratio of the PCB traces.
10. The method according to claim 9 wherein the L/C characteristic impedance ratio of the ESD circuit parasitics is adjusted using the ESD protection circuit.
11. A system for transmitting signals and discharging an electrostatic discharge (ESD) event pulse associated with an ESD event to ground to protect an integrated circuit device under protection comprising:
a printed circuit board (“PCB”) carrying a plurality of devices including the device under protection and an electrostatic discharge protection device separate from the device under protection, the printed circuit having a plurality of PCB trace lines that transmits signals between the plurality of devices, wherein at least one PCB trace line is formed of first and second line portions that are electrically isolated from one another,
wherein the electrostatic discharge protection device protects the device under protection from the ESD event and is adapted to transmit the signal from the first line portion to the second line portion,
wherein the electrostatic discharge protection device includes predetermined device parasitics that have an inductance/capacitance ratio that match inductance/capacitance ratio of the at least one PCB trace line, and
wherein the electrostatic discharge protection device comprises an integrated circuit having:
an input pad adapted for electrical coupling to the first line portion on the printed circuit board that receives the signal, and the ESD event pulse associated with the ESD event;
an output pad adapted for electrical coupling to the second line portion of the printed circuit board; and
an electrostatic discharge circuit connected between the input pad and the output pad, the electrostatic discharge circuit providing an electrical path for the signal from the input pad to the output pad and dissipating the ESD event pulse by providing a path to the ground.
12. The system according to claim 11 wherein the inductance/capacitance ratio of the device parasitics is adjusted using first and second bondwires that electrically connect the input pad to the first line portion and the output pad to the second line portion, respectively.
13. The system according to claim 12 , wherein the first and second bondwires are configured to have a parasitic inductance that cancels undesired capacitance of the PCB trace line.
14. The system according to claim 12 wherein the plurality of PCB trace lines provide a plurality of channels, and wherein a plurality of bondwires are matched with each other to assist in maintaining the device parasitics that have the inductance/capacitance that matches a PCB trace inductance/capacitance ratio associated with the plurality of PCB trace lines.
15. The system according to claim 11 wherein the inductance/capacitance ratio of the device parasitics is adjusted using the electrostatic discharge circuit.
16. The method according to claim 6 , further comprising:
mounting the device under protection on the PCB; and
mounting the ESD circuit on the PCB.
17. The method according to claim 16 wherein the step of providing provides the compensated ESD circuit device using first and second bondwires that electrically connect an input pad to a first line portion and an output pad to a second line portion, respectively.
18. The method according to claim 17 , wherein the first and second bondwires are configured to have a parasitic inductance that cancels undesired capacitance that exists from the PCB trace line.
19. The method according to claim 17 wherein the step of providing provides a plurality of PCB traces with a plurality of channels, and wherein a plurality of bondwires are matched with each other to assist in maintaining the device parasitics that have the L/C characteristic impedance ratio that matches the Lo/Co characteristic impedance ratio of the PCB traces.
20. The method according to claim 19 wherein the L/C characteristic impedance ratio of the device parasitics is adjusted using the electrostatic discharge circuit.