Method for manufacturing stack package using through-electrodes
View Patent ↗Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.
1. A method for manufacturing a wafer level stack package, comprising:
back-grinding a lower surface of a wafer comprising a plurality of first semiconductor chips, the first semiconductor chips being at a wafer level;
attaching a support member to a lower surface of the back-grinded wafer;
stacking one or more individual second semiconductor chips over corresponding ones of the first semiconductor chips by interposing an adhesive or an adhesive tape between adjacent stacked semiconductor chips of the first and second semiconductor chips;
forming first through-electrodes to electrically connect the first semiconductor chips to the corresponding one or more second semiconductor chips;
attaching third semiconductor chips to respective uppermost ones of the stacked second semiconductor chips, the third semiconductor chips having second through-electrodes electrically connected to the first through-electrodes and re-distribution lines electrically connected to the second through-electrodes;
attaching outside connection terminals to the re-distribution lines of the third semiconductor chips; and
sawing the first semiconductor chips of the wafer level having the corresponding second and third semiconductor chips stacked thereon, such that the first semiconductor chips are at a chip level.
2. The method for manufacturing a wafer level stack package according to claim 1 , wherein the support member comprises any one of glass and a wafer carrier.
3. The method for manufacturing a wafer level stack package according to claim 1 , further comprising the step of determining whether the first semiconductor chips of the back-grinded wafer are good dies,
wherein the second semiconductor chips are stacked only over the first semiconductor chips determined as good dies.
4. The method for manufacturing a wafer level stack package according to claim 1 , further comprising the step of:
after forming the first through-electrodes and before attaching the third semiconductor chips, removing the support member.
5. The method for manufacturing a wafer level stack package according to claim 1 , further comprising the step of:
after attaching the outside connection terminals and before sawing the first semiconductor chips such that the first semiconductor chips are at a chip level, removing the support member.
6. The method for manufacturing a wafer level stack package according to claim 1 , wherein the step of forming the first through-electrodes comprises the steps of:
etching the respective first semiconductor chips and the one or more second semiconductor chips stacked on the corresponding respective first semiconductor chips to define through-holes exposing the support member; and
filling a metallic material in the respective through-holes.
7. The method for manufacturing a wafer level stack package according to claim 6 , wherein the step of filling the metallic material comprises inserting metal pins or plating.
8. The method for manufacturing a wafer level stack package according to claim 1 , wherein each of the first, second and third semiconductor chips comprises the same kind of semiconductor chip each semiconductor chip having the same function.
9. The method for manufacturing a wafer level stack package according to claim 1 , wherein the first, second and third semiconductor chips each comprises a different kind of semiconductor chip each semiconductor chip having a different function.
10. A method for manufacturing a wafer level stack package, comprising:
providing a wafer including a plurality of first semiconductor chips, the first semiconductor chips being at a wafer level;
stacking one or more individual second semiconductor chips over corresponding ones of the first semiconductor chips of the wafer level by interposing an adhesive or an adhesive tape between adjacent stacked semiconductor chips of the first and second semiconductor chips;
forming first through-electrodes to electrically connect the first semiconductor chips to the corresponding one or more individual second semiconductor chips; and
sawing the first semiconductor chips of the wafer level having the corresponding individual second semiconductor chips stacked thereon, such that the first semiconductor chips are at a chip level.
11. The method for manufacturing a wafer level stack package according to claim 10 , further comprising the steps of:
attaching third semiconductor chips to respective uppermost ones of the stacked second semiconductor chips;
forming second through electrodes in the attached third semiconductor chip such that the second through electrodes are electrically connected to the first through electrodes;
forming re-distribution lines on the third semiconductor chip such that the re-distribution lines are electrically connected to the second through electrodes; and
attaching outside connection terminals to the re-distribution lines of the third semiconductor chips.
12. The method for manufacturing a wafer level stack package according to claim 11 , wherein the step of providing a wafer comprises the steps of:
back-grinding a lower surface of the wafer comprising the plurality of first semiconductor chips; and
attaching a support member to a lower surface of the back grinded wafer.
13. The method for manufacturing a wafer level stack package according to claim 12 , further comprising the steps of:
after forming the first through-electrodes and before attaching the third semiconductor chips, removing the support member.
14. The method for manufacturing a wafer level stack package according to claim 12 , further comprising the steps of:
after the step of attaching the outside connection terminals and before the step of sawing the first semiconductor chips such that the first semiconductor chips are at a chip level, removing the support member.
15. The method for manufacturing a wafer level stack package according to claim 10 , further comprising the step of determining whether the first semiconductor chips are good dies,
wherein the second semiconductor chips are stacked only on the first semiconductor chips determined as good dies.
16. The method for manufacturing a wafer level stack package according to claim 10 , wherein the step of forming the first through-electrodes comprises the steps of:
etching the respective first semiconductor chips and the one or more second semiconductor chips stacked on the corresponding respective first semiconductor chips to define through-holes exposing the support member; and
filling a metallic material in the respective through-holes.
17. The method for manufacturing a wafer level stack package according to claim 16 , wherein the step of filling the metallic material comprises inserting metal pins or plating.
18. The method for manufacturing a wafer level stack package according to claim 10 , wherein each of the first, second and third semiconductor chips comprise the same kind of semiconductor chips each having the same function or different kinds of semiconductor chips each having different functions.