Structure and method for back end of the line integration
View Patent ↗An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
1. A method of fabricating a semiconductor structure comprising:
providing an interconnect structure that includes a lower interconnect level comprising a first dielectric layer having at least one conductive feature embedded therein, an upper interconnect level comprising a second dielectric having at least one via opening that exposes a portion of said at least one conductive feature located atop said lower interconnect level, said lower and upper interconnect levels are partially separated by a dielectric capping layer, and a patterned hard mask on a surface of said upper interconnect level;
forming a first barrier layer on all exposed surfaces of said via opening;
removing said first barrier layer at a bottom of said via opening and on said patterned hard mask while maintaining said first barrier layer on remaining sidewall surfaces of said via opening;
forming a conductive protrusion in said at least one conductive feature, said conductive protrusion located at a bottom of said via opening and extends upward from bottom of said via opening and into said at least one via opening;
forming a seed layer within said at least one via opening, and;
filling said at least one via opening with a conductive material.
2. The method as in claim 1 , wherein said providing said interconnect structure includes forming at least one conductive feature within said first dielectric material, forming a blanket dielectric capping layer on said first dielectric material, forming said second dielectric material on said blanket dielectric capping layer, forming a patterned hard mask having via patterns on said second dielectric material, and transferring said via patterns into said second dielectric material and said blanket dielectric capping layer.
3. The method as in claim 1 , further comprising:
a forming a barrier layer step after said forming a conductive protrusion step and before said forming a seed layer step, said forming a barrier layer step comprising forming a second barrier layer on said first barrier layer and atop said conductive protrusion.
4. The method as in claim 1 , further comprises forming said first barrier layer with a material selected from a group consisting of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN and Co.
5. The method as in claim 3 , further comprises forming said second barrier layer with a material selected from a group consisting of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN and Co.
6. The method as in claim 1 , wherein said removing of said first barrier layer comprises sputtering directional gas selected from a group consisting of Ar, He, Ne, Xe, N 2 , H 2 , NH 3 , N 2 H 2 and mixtures thereof.
7. The method as in claim 1 , further comprises forming said conductive protrusion with PVD, CVD, ALD, electro plating, electroless plating, or combinations thereof.
8. The method as in claim 1 , further comprising said forming of said seed layer comprises depositing one or a combination of Ru, TaRu, Ir, Rh, Pt, Pd, Cu, Co or alloys thereof.
9. The method as in claim 1 , further comprising said filling said at least one via opening comprises depositing at least one of Cu, Al, W or alloys thereof.
10. The method as in claim 1 , further comprising:
a planarization step following said filling with said conductive material, wherein said planarization step provides a conductive filled via that having an upper surface coplanar with an upper surface of said second dielectric material.
11. A method of fabricating a semiconductor structure comprising:
providing an interconnect structure that includes a first dielectric layer having at least one conductive feature embedded therein, a second dielectric layer having at least one via opening that exposes a portion of said at least one conductive feature, said lower and upper interconnect levels are partially separated by a dielectric capping layer;
forming a first barrier layer on sidewalls of said via opening;
forming a conductive protrusion extending from said exposed portion and into said at least one via opening;
forming a seed layer within said at least one via opening, and;
filling said at least one via opening with a conductive material.
12. The method as in claim 11 , wherein said providing said interconnect structure includes forming at least one conductive feature within said first dielectric material, forming a blanket dielectric capping layer on said first dielectric material, forming said second dielectric material on said blanket dielectric capping layer, forming a patterned hard mask having via patterns on said second dielectric material, and transferring said via patterns into said second dielectric material and said blanket dielectric capping layer.
13. The method as in claim 11 , further comprising:
a forming a barrier layer step after said forming a conductive protrusion step and before said forming a seed layer step, said forming a barrier layer step comprising forming a second barrier layer on said first barrier layer and atop said conductive protrusion.
14. The method as in claim 11 , further comprises forming said first barrier layer with a material selected from a group consisting of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN and Co.
15. The method as in claim 13 , further comprises forming said second barrier layer with a material selected from a group consisting of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN and Co.
16. The method as in claim 11 , wherein said removing of said first barrier layer comprises sputtering directional gas selected from a group consisting of Ar, He, Ne, Xe, N 2 , H 2 , NH 3 , N 2 H 2 and mixtures thereof.
17. The method as in claim 11 , further comprises forming said conductive protrusion with PVD, CVD, ALD, electro plating, electroless plating, or combinations thereof.
18. The method as in claim 11 , further comprising said forming of said seed layer comprises depositing one or a combination of Ru, TaRu, Ir, Rh, Pt, Pd, Cu, Co or alloys thereof.
19. The method as in claim 11 , further comprising said filling said at least one via opening comprises depositing at least one of Cu, Al, W or alloys thereof.
20. The method as in claim 11 , further comprising:
a planarization step following said filling with said conductive material, wherein said planarization step provides a conductive filled via that having an upper surface coplanar with an upper surface of said second dielectric material.