Package-on-package system with through vias and method of manufacture thereof

1. A method of manufacture of a package-on-package system comprising:

providing a package substrate;

attaching a semiconductor die to the package substrate;

providing the package substrate includes forming the package substrate incorporating tie bars extending to edges of the package-on-package system;

forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface;

forming the encapsulant includes creating through openings located on one side of the tie bars; and

creating through vias by applying solder into the through openings.

2. A method of manufacture of a package-on-package system comprising:

providing a package substrate with substrate connections;

attaching a semiconductor die to the package substrate;

providing the package substrate includes forming the package substrate incorporating tie bars extending to edges of the package-on-package system;

connecting the semiconductor die to the substrate connections in the package substrate using electrical interconnects;

molding an encapsulant around the semiconductor die using a mold with pins to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface, wherein the pins define through openings extending from the top exposed surface through the bottom exposed surface; the molding an encapsulant includes creating through openings located on either side of the tie bars; and

creating through vias by applying solder through a stencil plate with openings aligned to the through openings.

3. A package-on-package system comprising:

a package substrate;

a semiconductor die attached to the package substrate;

the package substrate includes tie bars extending to edges of the package-on-package system;

an encapsulant surrounding at least portions of the package substrate and the semiconductor die, the encapsulant having a bottom exposed surface coplanar with the bottom surface of the package substrate and a top exposed surface; and

through vias extending from the top exposed surface to a bottom exposed surface of the encapsulant, the through vias being located on one side of the tie bars.

4. The system as claimed in claim 3 further comprising:

substrate connections defined in the package substrate;

electrical interconnects for connecting the semiconductor die to the substrate connections in the package substrate; and

wherein:

the encapsulant is a molding compound.

5. The system as claimed in claim 4 wherein:

the package substrate includes an offset between the tie bars; and

the through vias are located on either side of the tie bars.