Controlling select gate voltage during erase to improve endurance in non-volatile memory
View Patent ↗A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates.
1. A method for erasing at least one set of series-connected non-volatile storage elements formed on a substrate, the method comprising:
in a first time period, driving at least one select gate of the at least one set of series-connected non-volatile storage elements at a non-zero level;
in a second time period which follows the first time period, ramping up an erase voltage which is applied to the substrate while continuing to drive the at least one select gate at the non-zero level;
in a third time period which follows the second time period, continuing to ramp up the erase voltage, until the erase voltage reaches a final erase voltage level, while floating a voltage of a control gate of the at least one select gate; and
in a fourth time period which follows the third time period, driving the erase voltage at the final erase voltage level while continuing to float the voltage of the control gate of the at least one select gate.
2. The method of claim 1 , wherein:
the driving of the at least one select gate in the first and second time periods comprises connecting a voltage source to the control gate of the at least one select gate via a pass gate; and
the floating of the voltage of the control gate of the at least one select gate in the third and fourth time periods comprises cutting off the pass gate.
3. The method of claim 1 , wherein:
the erase voltage is ramped up starting from 0 V in the second time period.
4. The method of claim 1 , wherein:
the non-zero level is selected to achieved a desired maximum level of the voltage of the control gate when the voltage of the control gate is floated.
5. The method of claim 1 , wherein:
the driving the at least one select gate at the non-zero level in the first time period, and the continuing to drive the at least one select gate at the non-zero level in the second time period, comprise driving at least one of a source side select gate and a drain side select gate of the at least one set of series-connected non-volatile storage elements.
6. The method of claim 2 wherein:
the cutting off the pass gate comprises
lowering a voltage applied to a control gate of the pass gate at a start of the third time period.
7. The method of claim 1 , wherein:
the second time period directly follows the first time period, the third time period directly follows the second time period, and the fourth time period directly follows the third time period.
8. A method for erasing at least one set of series-connected non-volatile storage elements formed on a substrate, the method comprising:
in a first time period, ramping up an erase voltage which is applied to the substrate from an initial level to a first level;
in a second time period which follows the first time period, driving the erase voltage at the first level;
driving at least one select gate of the at least one set of series-connected non-volatile storage elements during the first and second time periods;
in a third time period which follows the second time period, ramping up the erase voltage further to a second level, while floating a voltage of a control gate of the at least one select gate; and
in a fourth time period which follows the third time period, driving the erase voltage at the second level, while continuing to float the voltage of the control gate of the at least one select gate.
9. The method of claim 8 , wherein:
during the first and second time periods, the at least one select gate is driven at a constant first, non-zero level.
10. The method of claim 8 , wherein:
the second time period directly follows the first time period, the third time period directly follows the second time period, and the fourth time period directly follows the third time period.
11. The method of claim 8 , wherein:
the initial level of the erase voltage is 0 V.
12. An apparatus which performs the method of claim 1 .
13. An apparatus which performs the method of claim 8 .
14. The method of claim 1 , wherein:
in the third time period, the voltage of the control gate of the at least one select gate floats up as the erase voltage ramps up.
15. The method of claim 1 , wherein:
in the fourth time period, the voltage of the control gate of the at least one select gate floats at a final, non-zero level as the erase voltage is driven at the final erase voltage level.
16. The method of claim 8 , wherein:
in the third time period, the voltage of the control gate of the at least one select gate floats up as the erase voltage ramps up.
17. The method of claim 8 , wherein:
in the fourth time period, the voltage of the control gate of the at least one select gate floats at a final, non-zero level as the erase voltage is driven at the second level.