Memory cell that employs a selectively fabricated carbon nano-tube reversible resistance-switching element formed over a bottom conductor and methods of forming the same
View Patent ↗In some aspects, a method of fabricating a memory cell is provided that includes: (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (“CNT”) material above the first conductor by: (a) fabricating a CNT seeding layer on the first conductor, wherein the CNT seeding layer comprises silicon-germanium (“Si/Ge”), (b) planarizing a surface of the deposited CNT seeding layer, and (c) selectively fabricating CNT material on the CNT seeding layer; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.
1. A memory cell comprising:
a first conductor;
a silicon-germanium layer above the first conductor;
a reversible resistance-switching element including resistance-switching carbon nano-tube (“CNT”) material selectively fabricated on the silicon-germanium layer;
a diode formed above the reversible resistance-switching element; and
a second conductor formed above the diode.
2. The memory cell of claim 1 , wherein the CNT material includes CNTs that are substantially vertically aligned to reduce lateral conduction in the CNT material.
3. The memory cell of claim 1 , wherein the CNT material includes defects that tune the switching characteristics of the CNT material.
4. The memory cell of claim 1 , wherein the diode comprises a vertical polycrystalline diode.
5. The memory cell of claim 1 , further comprising a silicide, silicide-germanide or germanide region in contact with polycrystalline material of the vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.
6. A plurality of nonvolatile memory cells comprising:
a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction;
a plurality of diodes;
a plurality of reversible resistance-switching elements, each reversible resistance-switching element comprising:
a silicon-germanium layer fabricated above one of first conductors; and
a resistance-switching carbon nano-tube (“CNT”) material layer selectively fabricated on the silicon-germanium layer; and
a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction different from the first direction; and
wherein, in each memory cell, one of the diodes is formed above one of the reversible resistance-switching elements, disposed between one of the first conductors and one of the second conductors.
7. The plurality of memory cells of claim 6 , wherein the CNT material layer includes CNTs that are substantially vertically aligned so as to reduce lateral conduction in the CNT material.
8. The plurality of memory cells of claim 6 , wherein the CNT material layer extends between two or more of the memory cells and forms the reversible resistance-switching element of the two or more memory cells.
9. The plurality of memory cells of claim 6 , wherein each diode is a vertical polycrystalline diode.
10. The plurality of memory cells of claim 6 , further comprising silicide, silicide-germanide or germanide in contact with polycrystalline material of each vertical polycrystalline diode so that the polycrystalline material is in a low-resistivity state.
11. A monolithic three dimensional memory array comprising:
a first memory level formed above a substrate, the first memory level comprising:
a plurality of memory cells, wherein each memory cell of the first memory level comprises:
a first conductor;
a reversible resistance-switching element including a silicon-germanium layer fabricated above the first conductor, and a resistance-switching carbon nano-tube (“CNT”) material layer selectively fabricated on the silicon-germanium layer; and
a diode formed above the reversible resistance-switching element; and
a second conductor formed above the diode; and
at least a second memory level monolithically formed above the first memory level.
12. The monolithic three dimensional memory array of claim 11 , wherein the CNT material layer of each reversible resistance-switching element includes CNTs that are substantially vertically aligned so as to reduce lateral conduction in the CNT material.
13. The monolithic three dimensional memory array of claim 11 , wherein the CNT material layer extends between two or more of the memory cells and forms the reversible resistance-switching element of the two or more memory cells.
14. The monolithic three dimensional memory array of claim 11 , wherein each diode comprises a vertical polycrystalline diode.
15. The monolithic three dimensional memory array of claim 14 , wherein each vertical polycrystalline diode comprises a vertical polysilicon diode.