IP Library Granted Patent US 8,710,634
Granted Patent B2
US 8,710,634 · App. 12/410,945 · Granted Apr 29, 2014

Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof

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Quick Facts
Patent No.
US 8,710,634
App. No.
12/410,945
Granted
Apr 29, 2014
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an integrated circuit above and to the substrate; mounting an internal interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate and over the integrated circuit with the integral-interposer-structure connected to the internal interconnect; and encapsulating the internal interconnect and the integrated circuit with an encapsulation.

Claims (26)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate having a plurality of substrate-interconnects;

mounting a plurality of internal interconnects to and over the plurality of substrate-interconnects;

mounting an integrated circuit above the substrate and the plurality of substrate-interconnects, the integrated circuit adjacent to and between the plurality of internal interconnects;

mounting an interposer having an integral-interposer-structure over the substrate, the plurality of substrate-interconnects, the integrated circuit and the plurality of internal interconnects, the integral-interposer-structure extending past peripheral sides of the integrated circuit and electrically connected to the plurality of internal interconnects, wherein mounting the interposer includes mounting an integral-conductive-shield having a hole;

embedding a die in the integral-interposer-structure between a top surface and a bottom surface of the integral-interposer-structure; and

forming an encapsulation encapsulating the plurality of internal interconnects and the integrated circuit.

2. The method as claimed in claim 1 wherein mounting the plurality of internal interconnects includes mounting each of the plurality of internal interconnects having a stand-off-height from the integrated circuit to the integral-conductive-shield.

3. The method as claimed in claim 1 wherein mounting the interposer further includes forming a grounding path from the integral-conductive shield through the plurality of internal interconnects, with the grounding path extending over and across the integrated circuit.

4. The method as claimed in claim 1 further comprising:

mounting an external interconnect to and under each of the plurality of substrate-interconnects.

5. The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting a flip-chip.

6. The method as claimed in claim 1 further comprising

mounting a passive component between the substrate and the integral-interposer-structure.

7. An integrated circuit packaging system comprising:

a substrate having a plurality of substrate-interconnects;

a plurality of internal interconnects mounted to and over the plurality of substrate-interconnects;

an integrated circuit mounted above the substrate and the plurality of substrate-interconnects, the integrated circuit adjacent to and between the plurality of internal interconnects;

an interposer having an integral-interposer-structure mounted over the substrate, the plurality of substrate-interconnects, the integrated circuit and the plurality of internal interconnects, the integral-interposer-structure extending past peripheral sides of the integrated circuit and electrically connected to the plurality of internal interconnects, the integral-interposer-structure having a die embedded in the integral-interposer-structure between a top surface and a bottom surface of the integral-interposer-structure, wherein the integral-interposer-structure is an integral-conductive-shield having a hole; and

an encapsulation encapsulating the plurality of internal interconnects and the integrated circuit.

8. The system as claimed in claim 7 wherein each of the plurality of internal interconnects includes a stand-off-height from the integrated circuit to the integral-conductive-shield.

9. The system as claimed in claim 7 further comprising a ground path from the integral-conductive shield through the plurality of internal interconnects with the ground path extending over and across the integrated circuit.

10. The system as claimed in claim 7 further comprising:

an external interconnect mounted to each of the plurality of substrate-interconnects.

11. The system as claimed in claim 7 wherein the integrated circuit is a flip-chip.

12. The system as claimed in claim 7 further comprising a passive component mounted above the substrate and under the integral-interposer-structure.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0227. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0368 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →