Multi-chip package
View Patent ↗A multi-chip package is presented which includes a substrate, a lower semiconductor, an upper semiconductor chip, metal wires, an encapsulant, and mounting units. The substrate has electrode terminals on an upper surface and ball lands on a lower surface. The lower semiconductor chip is placed face-down on the substrate. The lower semiconductor chip has first bonding pads, first connectors and metal patterns. The upper semiconductor chip is placed face-down type on the back surface of the lower semiconductor chip. The upper semiconductor has second bonding pads and second connectors. The metal wires electrically the lower semiconductor chip to the substrate. The encapsulant seals the substrate, the lower semiconductor chip, the upper semiconductor chip and the metal wires. The mounting units are on the lower surface of the substrate.
1. A multi-chip package comprising:
a substrate including:
electrode terminals on an upper surface of the substrate, and
ball lands on a lower surface of the substrate;
a lower semiconductor chip placed face-down on the substrate, the lower semiconductor chip including:
first bonding pads on a front surface, and
first connectors electrically and mechanically connecting together the first bonding pads of the lower semiconductor chip to the electrode terminals of the substrate; and
metal patterns on a back surface of the lower semiconductor chip;
an upper semiconductor chip placed face-down type on the back surface of the lower semiconductor chip, the upper semiconductor including:
second bonding pads on a frontal surface of the upper semiconductor, and
second connectors electrically and mechanically connecting the second bonding pads of the upper semiconductor chip and the metal patterns;
metal wires electrically connecting together the metal patterns of the lower semiconductor chip and the electrode terminals of the substrate;
an encapsulant sealing the upper surface of the substrate, the lower semiconductor chip, the upper semiconductor chip and the metal wires; and
mounting units on the ball lands which are on the lower surface of the substrate wherein the first and second bonding pads each comprise an adhesive layer, a diffusion barrier layer and a wetting layer.
2. The multi-chip package according to claim 1 , wherein the first connectors comprise bump first connectors or solder ball first connectors.
3. The multi-chip package according to claim 1 , wherein the lower semiconductor chip and the upper semiconductor chip have substantially the same size.
4. The multi-chip package according to claim 1 , wherein the lower semiconductor chip and the upper semiconductor chip have different sizes.
5. The multi-chip package according to claim 1 , wherein the lower semiconductor chip and the upper semiconductor chip are edge pad type semiconductor chips.
6. The multi-chip package according to claim 1 , wherein the lower semiconductor chip and the upper semiconductor chip are center pad type semiconductor chips.
7. The multi-chip package according to claim 1 , wherein the second connectors comprise bump second connectors or solder ball second connectors.
8. The multi-chip package according to claim 1 , further comprises a filler material between the substrate and the lower semiconductor chip.
9. The multi-chip package according to claim 1 , wherein the adhesive layer is formed of Al, Ti or Cr.
10. The multi-chip package according to claim 1 , wherein the diffusion barrier layer is formed of Ni.
11. The multi-chip package according to claim 1 , wherein the wetting layer is formed of Au, Cu, or Pd.