Gate trim process using either wet etch or dry etch approach to target CD for selected transistors
View Patent ↗Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
1. A method for forming a semiconductor device having transistors with targeted CDs, comprising:
providing a semiconductor device comprising a hard mask layer formed over a gate material layer, wherein the hard mask layer is formed into a plurality of hard mask lines and a layer of spacer material formed over the plurality of hard mask lines;
covering a first portion of the plurality of hard mask lines with a first resist;
performing a wet etch process on the semiconductor device having the first portion of the plurality of hard mask lines covered with a first mask;
removing the first resist from the first portion of the plurality of hard mask lines;
performing a first dry etch process to remove a portion of the spacer material, wherein the remaining spacer material adheres to the sides of the plurality of hard mask lines to form sidewall spacers; and
after performing the first dry etch, covering a second portion of the plurality of hard mask lines and associated spacer sidewalls with a second resist and performing a second dry etch to remove substantially all of sidewall spacers from the portion of the plurality of hard mask lines not covered by the second resist.
2. The method of claim 1 , wherein performing the dry etch process forms a semiconductor device precursor having the width of the sidewall spacers associated with at least one of the plurality of hard mask lines substantially different from the width of sidewall spacers associated with another hard mask line.
3. The method of claim 1 , wherein performing the dry etch process forms a semiconductor device precursor having the width of the sidewall spacers associated with at least one of the plurality of hard mask lines different from the width of sidewall spacers associated with another hard mask line by about 4 nm or more.
4. The method of claim 1 , wherein performing the dry etch process forms a semiconductor device precursor having the width of the sidewall spacers associated with at least one of the plurality of hard mask lines different from the width of sidewall spacers associated with another hard mask line from about 5 nm to about 35 nm.
5. The method of claim 1 , wherein the width of sidewall spacers associated with a first hard mask line is about 5 nm or more narrower than the width of sidewall spacers associated with a second hard mask line, wherein a third hard mask line has substantially no associated sidewall spacers.
6. The method of claim 1 , further comprising contacting the gate material layer with an etchant to form gate lines and the semiconductor device has the width of at lest one gate line different from the width of another gate line by about 5 nm or more.
7. The method of claim 6 , wherein contacting of the gate material with an etchant forms a semiconductor device having the width of at lest one gate line different from the width of another gate line from about 5 nm to about 35 nm.
8. The method of claim 1 , wherein the widths of the plurality of hard mask lines are substantially equal.
9. The method of claim 1 , wherein the width of sidewall spacers associated with a first hard mask line is about 5 nm to about 25 nm narrower than the width of sidewall spacers associated with a second hard mask line.
10. The method of claim 2 , wherein the width of sidewall spacers associated with a first hard mask line is about 5 nm to about 25 nm narrower than the width of sidewall spacers associated with a second hard mask line.
11. The method of claim 2 , wherein the widths of the plurality of hard mask lines are substantially equal.
12. A method for forming a semiconductor device having transistors with targeted CDs, comprising:
providing a semiconductor device comprising a hard mask layer formed over a gate material layer, wherein the hard mask layer is formed into a plurality of hard mask lines and a layer of spacer material formed over the plurality of hard mask lines;
covering a first portion of the plurality of hard mask lines with a first resist;
performing a wet etch process on the semiconductor device having the first portion of the plurality of hard mask lines covered with a first mask;
removing the first resist from the first portion of the plurality of hard mask lines;
performing a first dry etch process to remove a portion of the spacer material, wherein the remaining spacer material adheres to the sides of the plurality of hard mask lines to form sidewall spacers;
after performing the first dry etch, covering a second portion of the plurality of hard mask lines and associated spacer sidewalls with a second resist and performing a second dry etch to remove substantially all of sidewall spacers from the portion of the plurality of hard mask lines not covered by the second resist; and
contacting the gate material layer with an etchant to form gate lines.
13. The method of claim 12 , wherein performing the dry etch process forms a semiconductor device precursor having the width of the sidewall spacers associated with at least one of the plurality of hard mask lines substantially different from the width of sidewall spacers associated with another hard mask line.
14. The method of claim 12 , wherein performing the dry etch process forms a semiconductor device precursor having the width of the sidewall spacers associated with at least one of the plurality of hard mask lines different from the width of sidewall spacers associated with another hard mask line by about 5 nm or more.
15. The method of claim 12 , wherein the semiconductor device has the width of at lest one gate line different from the width of another gate line by about 5 nm or more.
16. The method of claim 15 , wherein contacting of the gate material with an etchant forms a semiconductor device having the width of at lest one gate line different from the width of another gate line from about 5 nm to about 35 nm.
17. The method of claim 12 , wherein the widths of the plurality of hard mask lines are substantially equal.
18. The method of claim 13 , wherein the widths of the plurality of hard mask lines are substantially equal.
19. A method for forming a semiconductor device having transistors with targeted CDs, comprising:
providing a semiconductor device comprising a hard mask layer formed over a gate material layer, wherein the hard mask layer is formed into a plurality of hard mask lines and a layer of spacer material formed over the plurality of hard mask lines;
covering a first portion of the plurality of hard mask lines with a first resist;
performing a wet etch process on the semiconductor device having the first portion of the plurality of hard mask lines covered with a first mask;
removing the first resist from the first portion of the plurality of hard mask lines;
performing a first dry etch process to remove a portion of the spacer material, wherein the remaining spacer material adheres to the sides of the plurality of hard mask lines to form sidewall spacers; and
after performing the first dry etch, covering a second portion of the plurality of hard mask lines and associated spacer sidewalls with a second resist and performing a second dry etch to remove substantially all of sidewall spacers from the portion of the plurality of hard mask lines not covered by the second resist,
wherein the semiconductor device has the width of at lest one gate line different from the width of another gate line by about 5 nm or more.
20. The method of claim 19 , wherein the widths of the plurality of hard mask lines are substantially equal.