IP Library Granted Patent US 8,012,818
Granted Patent B2
US 8,012,818 · App. 12/439,584 · Granted Sep 6, 2011

Method for improving inversion layer mobility in a silicon carbide MOSFET

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,012,818
App. No.
12/439,584
Granted
Sep 6, 2011
Kind
B2
Abstract

A method of manufacturing a semiconductor device based on a SiC substrate involves forming an oxide layer on a Si-terminated face of the SiC substrate at an oxidation rate sufficiently high to achieve a near interface trap density below 5×10 11 cm −2 ; and annealing the oxidized SiC substrate in a hydrogen-containing environment, to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET having improved inversion layer mobility and reduced threshold voltage. It has been found that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. The deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.

Claims (19)

1. A method of manufacturing a semiconductor device based on a SiC substrate, comprising:

forming an oxide layer on a Si-terminated face of said SiC substrate at an oxidation rate sufficiently high to achieve a near interface trap density below 5×10 11 cm −2 ; and

annealing said oxidized SiC substrate in a hydrogen-containing environment, in order to passivate deep traps formed in said oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET having improved inversion layer mobility and reduced threshold voltage.

2. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 1 , wherein said oxidation rate has a maximum which is at least 700 Angstrom per hour at a temperature of 1150 degrees C.

3. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 1 , wherein said sufficiently high oxidation rate is achieved by means of an oxidation rate enhancing agent.

4. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 3 , wherein said oxidation rate enhancing agent is introduced in an oxidation chamber during oxidation of said Si-terminated face of said SiC substrate.

5. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 3 , wherein said oxidation rate enhancing agent is an alkali metal.

6. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 5 , wherein said oxidation rate enhancing agent is sodium.

7. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 1 , wherein said oxide-forming step comprises:

providing said SiC substrate in an oxidation chamber; and

introducing sodium into said oxidation chamber during oxidation of a Si-terminated face of said SiC-substrate, thereby achieving a sufficiently high oxidation rate to reduce the density of near interface traps to below 5×10 11 cm −2 .

8. The method of manufacturing a semiconductor device based on a SiC substrate according to claim 7 , wherein said annealing step comprises:

subjecting said oxidized SiC substrate to a first post-oxidation anneal in an inert gas, to reduce an amount of mobile sodium in said oxidized SiC substrate; and

subjecting said sodium reduced oxidized SiC substrate to a second post-oxidation anneal in a hydrogen-containing environment, in order to passivate said deep traps.

9. A semiconductor device comprising:

a SiC substrate having a Si-terminated face; and

an oxide layer formed on said Si-terminated face of said SiC substrate, wherein:

a concentration of near interface traps at an interface between said SiC substrate and said oxide is lower than 5×10 11 cm −2 ; and

a concentration of passivated deep traps at said interface is in excess of 10 12 cm −2 .

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
PATENT RELEASE Recorded Apr 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.; MIZUHO BANK, LTD.
To: NXP B.V.
Reel/Frame 038400/0637 →
CERTIFICATE RE. TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Apr 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.; MIZUHO BANK, LTD.
To: NXP B.V.
Reel/Frame 038401/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2016
From: NXP B.V.
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 037973/0107 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2009
From: ROEDLE, THOMAS C.; SVIENBJORNSSON, EINAR O.; ALLERSTAM, CARL F.; OLAFSSON, HALLDOR O.; GUDJONSSON, GUDJON I.
To: NXP, B.V.
Reel/Frame 022330/0132 →