Implantation using a hardmask
View Patent ↗A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
1. A method for multiple ion implantations, comprising:
forming and patterning a hardmask over a substrate, wherein said hardmask attains a first opening;
performing a first ion implantation, wherein outside said first opening said hardmask is essentially preventing ions from reaching said substrate;
ensuing said first ion implantation, applying a photoresist, wherein said photoresist is covering said hardmask and is filling said first opening;
using said photoresist to pattern said hardmask, wherein said hardmask attains a second opening; and
performing a second ion implantation, wherein outside said second opening said hardmask and said photoresist are essentially preventing ions from reaching said substrate.
2. The method of claim 1 , wherein said method further comprises selecting a semiconductor substrate as said substrate.
3. The method of claim 2 , wherein said method further comprises selecting ions of said first ion implantation to comprise first type dopant impurities, and selecting ions of said second ion implantation to comprise second type dopant impurities.
4. The method of claim 3 , wherein said first opening defines a first well of a CMOS circuit, and said second opening defines a second well of said CMOS circuit.
5. The method of claim 4 , wherein said method further comprises selecting said first type dopant impurities as n-type, selecting said second type dopant impurities as p-type, wherein said first well is an n-well, and said second well is a p-well.
6. The method of claim 4 , wherein said method further comprises selecting said first type dopant impurities as p-type, selecting said second type dopant impurities as n-type, wherein said first well is a p-well, and said second well is an n-well.
7. The method of claim 1 , wherein said method further comprises disposing a pad layer onto said substrate before forming said hardmask.
8. The method of claim 1 , further comprising:
until a predetermined number of ion implantations have been performed, repeating the steps of:
applying an additional photoresist;
using said additional photoresist, patterning said hardmask, wherein creating an additional opening;
performing an additional ion implantation;
wherein outside said additional opening said hardmask and said additional photoresist are essentially preventing ions from reaching said substrate.
9. A method for processing a CMOS circuit, comprising:
forming and patterning a hardmask over a semiconductor substrate, wherein said hardmask is opened up in a first portion of said CMOS circuit;
performing a first ion implantation comprising first type of dopant impurities, wherein outside said first portion said hardmask is essentially preventing said first type of dopant impurities from reaching said semiconductor substrate;
ensuing said first ion implantation, applying a photoresist, wherein said photoresist is covering said hardmask and is masking said first portion;
using said photoresist to pattern said hardmask, wherein said hardmask is opened up in a second portion of said CMOS circuit;
performing a second ion implantation comprising second type of dopant impurities, wherein outside said second portion said hardmask and said photoresist are essentially preventing said second type of dopant impurities from reaching said semiconductor substrate;
selecting said first and second portions to be wells for said CMOS circuit.
10. The method of claim 9 , wherein said method further comprises selecting said first type dopant impurities as n-type, and selecting said second type dopant impurities as p-type.
11. The method of claim 9 , wherein said method further comprises selecting said first type dopant impurities as p-type, and selecting said second type dopant impurities as n-type.
12. The method of claim 9 , wherein said hardmask is chosen to comprise an oxide.
13. The method of claim 12 , wherein said method further comprises disposing a pad layer onto said semiconductor substrate before forming said hardmask.
14. The method of claim 13 , wherein said pad layer is chosen to comprise nitride.
15. The method of claim 9 , wherein said hardmask is chosen to comprise nitride.
16. A method for fabricating a CMOS circuit, comprising:
forming a hardmask over a semiconductor substrate, wherein said hardmask has a thickness;
patterning an opening in said hardmask, and selecting said opening to define a well for said CMOS circuit, wherein said opening has a minimal lateral dimension, and selecting the ratio of said thickness to said minimal lateral dimension to be greater than 1; and
implanting dopant impurities, wherein outside said opening said hardmask is essentially preventing said dopant impurities from reaching said substrate.
17. The method of claim 16 , wherein said hardmask is chosen to comprise an oxide.
18. The method of claim 17 , wherein said method further comprises disposing a nitride pad layer onto said semiconductor substrate before forming said hardmask.
19. The method of claim 16 , wherein said method further comprises selecting said dopant impurities as n-type.
20. The method of claim 16 , wherein said method further comprises selecting said dopant impurities as p-type.