Wire bond and redistribution layer process
View Patent ↗A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.
1. A semiconductor apparatus comprising:
a semiconductor substrate, the substrate including a plurality of devices, some of which are electrically connected together, some of which are ESD protection devices, and some of which are filtering devices;
a plurality of layers disposed over the semiconductor substrate, at least one of the layers being an insulating layer and at least another of the layers being a conducting aluminum layer, the conducting aluminum layer including aluminum wiring that electrically interconnects at least some of the plurality of devices, a plurality of internal wire bond pads and a plurality of external wire bond pads; and
a copper redistribution line disposed within an insulating redistribution layer, the redistribution layer disposed over the plurality of layers, the copper redistribution line interconnecting at least some of the internal wire bond pads and further including at least one copper inductor, wherein
vertical portions of the insulating distribution layer and corresponding vertical portions of the insulating layer are removed in order to expose the plurality of external wire bond pads yet maintain the copper redistribution line and the copper inductor covered.
2. The apparatus of claim 1 , further comprising a conducting material that fills each of the vertical portions, thereby connecting the external wire bond pads to the external connection lines.
3. The apparatus of claim 2 wherein the copper inductor can provide a range of impedance from 3 nanohenries to 50 nanohenries.
4. The apparatus of claim 3 wherein the apparatus has a range of filtering operation from 3 gigahertz to 10 gigahertz.
5. The apparatus of claim 4 wherein the amount of ESD protected by the ESD protection devices is +/−15 kilo electron volt (IEC) to +/−30 kilo electron volt (HBM).
6. A semiconductor device comprising:
a semiconductor substrate having a plurality of devices provided thereon, the plurality of devices including a plurality of electrically connected devices, one or more ESD protection devices and one or more filtering devices;
a plurality of layers disposed over the semiconductor substrate, including at least one insulating layer, a top insulating layer and a conducting layer, the conducting layer including aluminum wiring that electrically interconnects at least some of the plurality of electrically connected devices, a plurality of internal wire bond pads and a plurality of external wire bond pads;
an insulating redistribution layer disposed over the top layer, wherein the insulating redistribution layer includes at least one copper redistribution line that interconnects at least some of the internal wire bond pads;
vertical portions extending from the plurality of external wire bond pads through one or more of the at least one insulating layer and the top insulating layer and through corresponding vertical portions of the insulating redistribution layer, wherein the vertical portions are formed by removal of material from the one or more of the at least one insulating layer, the top insulating layer and the insulating redistribution layer;
conducting material filling each of the vertical portions, the conducting material connecting external wire bond pads to associated external connection lines; and
a copper inductor formed within the insulating redistribution layer.
7. The semiconductor device of claim 6 , wherein the copper redistribution line and the copper inductor are insulated from the conducting material filling each of the vertical portions.
8. The semiconductor device of claim 7 , wherein the vertical portions are filled with the conducting material in a manufacturing operation that is separate and subsequent to manufacturing operations that form the semiconductor substrate, the plurality of layers disposed over the semiconductor substrate the insulating redistribution layer, the vertical portions and the copper inductor.
9. The semiconductor device of claim 8 wherein the copper inductor has an impedance of at least 3 nanohenries.
10. The semiconductor device of claim 9 wherein the impedance is less than 50 nanohenries.
11. The semiconductor device of claim 8 wherein the filtering devices include a device that operates an operating frequency greater than 3 gigahertz.
12. The semiconductor device of claim 11 wherein the operating frequency is less than 10 gigahertz.