Process of forming an electronic device including a well region

1. A process of forming an electronic device including an integrated circuit comprising:

providing a substrate that includes a semiconductor layer overlying a buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region lies closer to the opposing surface than to the primary surface;

forming a first doped structure within the semiconductor layer, wherein the first doped structure, from a cross-sectional view, is a U-shaped structure, has a horizontal portion that lies closer to the opposing surface than to the primary surface, and has an opposite conductivity type as compared to the buried conductive region; and

forming a first vertical conductive structure extending through the semiconductor layer, wherein, in a finished device:

a first well region includes a first portion of the semiconductor layer that is defined by and overlies the first doped structure; and

the buried conductive region, the first doped structure, and the first vertical conductive structure are electrically connected to one another.

2. The process of claim 1 , wherein providing the substrate and forming the first doped structure comprise:

providing a substrate that includes a first part of the semiconductor layer over the buried conductive region;

selectively doping the first part of the semiconductor layer to form a first horizontal portion of the first doped structure;

epitaxially growing a second part of the semiconductor layer; and

selectively doping the second part of the semiconductor layer to form a first vertical portion of the first doped structure.

3. The process of claim 1 , further comprising:

forming a second well region that includes a second portion of the semiconductor layer, wherein the second well region has an opposite conductivity type as compared to the first well region.

4. The process of claim 3 , further comprising:

forming a second horizontal portion of a second doped structure within the semiconductor layer, wherein the second horizontal portion is spaced apart from the buried conductive region; and

forming a second vertical portion of the second doped structure, wherein the second vertical portion lies between the second horizontal portion and the primary surface of the semiconductor layer,

wherein, in a finished device;

the second well region further includes the second doped structure;

the second doped structure surrounds and has a higher dopant concentration than the second portion of the semiconductor layer; and

the second well region is spaced apart from the buried conductive region.

5. The process of claim 3 , further comprising forming a third well region that includes a third portion of the semiconductor layer, wherein the third well region is spaced apart from the first and second well regions.

6. The process of claim 5 , further comprising forming a fourth well region that includes a fourth portion of the semiconductor layer, wherein the fourth well region is spaced apart from the first, second, and third well regions.

7. The process of claim 6 , wherein:

the first well region is a p-well region;

the second well region is an n-well region;

the third well region is another p-well region and is spaced apart from the buried conductive region; and

the fourth well region is another n-well region and is spaced apart from the buried conductive region.

8. The process of claim 7 , further comprising:

forming a first electronic component within the first well region, wherein the first electronic component is part of a first control circuit;

forming a second electronic component within the second well region, wherein the second electronic component is part of the first control circuit;

forming a third electronic component within the third well region, wherein the third electronic component is part of a second control circuit;

forming a fourth electronic component within the fourth well region, wherein the fourth electronic component is part of the second control circuit;

forming a first current-carrying electrode, a second current-carrying electrode, and a first control electrode of a first power transistor;

forming a third current-carrying electrode, a fourth current-carrying electrode, and a second control electrode of a second power transistor;

coupling the second current-carrying electrode and the third current-carrying electrode to the buried conductive region;

coupling the first control circuit to the first control electrode;

coupling the second control circuit to the second control electrode;

coupling the first current-carrying electrode to a first terminal; and

coupling the fourth current-carrying electrode to a second terminal designed to operate at a different voltage than the first terminal.

9. A process of forming an electronic device including an integrated circuit having a first section, a second section, a third section, and a fourth section, the process comprising:

providing a substrate that includes a semiconductor layer overlying a buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface, the semiconductor layer has a first conductivity type, and the buried conductive region lies closer to the opposing surface than to the primary surface;

forming a first buried doped region;

forming first doped vertical portions within the first, second, and fourth sections, wherein:

first doped structures include combinations of the first buried doped regions and the first doped vertical portions that define first interior portions of the semiconductor layer;

the first doped structure within the first section defines a first well region; and

a first doped structure is not formed within the third section;

forming second buried doped regions within the second and fourth sections;

forming second doped vertical portions within the second and fourth sections, wherein:

second doped structures include combinations of the second buried doped regions and the second doped vertical portions that define second interior portions of the semiconductor layer;

second well regions include combinations of the second doped structure and the second interior portions;

each of the second well regions has a second conductivity type opposite that of the first conductivity type; and

each of the second doped structures has a higher dopant concentration as compared to the second interior portions; and

forming a third buried doped region within the third section; and

forming a third doped vertical portion within the third section, wherein:

a third doped structure includes a combination of the third buried doped region and the third doped vertical portion that defines a third interior portion of the semiconductor layer;

a third well region includes a combination of the third doped structure and the third interior portion;

the third well region has the first conductivity type; and

the third doped structure has a higher dopant concentration as compared to the third interior portion.

10. The method of claim 9 , further comprising forming vertical conductive structures extending through the semiconductor layer, and, in a finished device, the buried conductive region and the vertical conductive structures are electrically connected to one another.

11. The method of claim 9 , wherein forming the first buried doped region, forming the first doped vertical portions, forming second buried doped regions, and forming second doped vertical portions are performed such that, within each of the second and fourth sections, the first doped structure is spaced apart from the second doped structure.

12. The method of claim 9 , wherein the first and third well regions are p-well regions, and the second and fourth well regions are n-well regions.