Integrated circuit with upstanding stylus
View Patent ↗A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer.
1. A method of forming an integrated circuit (IC) including at least one stylus, said method comprising the steps of:
a) forming an orifice in a surface layer of a layered wafer;
b) forming a tip mold in said orifice, said tip mold having a circular cross section decreasing in diameter from top to bottom;
c) filling said tip mold with tip material, the tip of a stylus forming in said filled tip mold; and
d) removing excess tip material from an upper surface of said surface layer.
2. A method of forming an IC as in claim 1 , wherein the step (b) of forming the tip mold comprises the steps of:
i) forming a conformal layer on a surface layer of said layered wafer;
ii) removing horizontal portions of said conformal layer from said surface layer; and
iii) repeating steps (i) and (ii) until said tip mold is formed.
3. A method of forming an IC as in claim 2 , wherein each succeeding said conformal layer is formed thinner than its immediately preceding layer.
4. A method of forming an IC as in claim 3 , wherein steps (i) and (ii) are repeated three times, such that a layered tip mold is formed from four concentric spacer layers.
5. A method of forming an IC as in claim 4 , wherein the step (ii) of removing horizontal portions comprises etching said conformal layer with a plasma etch having an enhanced sputtering component.
6. A method of forming an IC as in claim 5 , wherein the step (ii) of removing horizontal portions comprises biasing said layered wafer during said plasma etch, biasing said layered wafer enhancing sputtering.
7. A method of forming an IC as in claim 6 , wherein said layered wafer is self biased.