IP Library Granted Patent US 8,148,052
Granted Patent B2
US 8,148,052 · App. 12/514,777 · Granted Apr 3, 2012

Double patterning for lithography to increase feature spatial density

Assignee: NXP B.V.
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Quick Facts
Patent No.
US 8,148,052
App. No.
12/514,777
Granted
Apr 3, 2012
Kind
B2
Abstract

A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.

Claims (44)

1. A method of forming a pattern in at least one device layer in or on a substrate comprising the steps of:

a) coating the device layer with a first photoresist layer;

b) exposing the first photoresist using a first mask;

c) developing the first photoresist layer to form a first pattern on the substrate;

d) coating the substrate with a protection layer;

e) treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step;

f) coating the substrate with a second photoresist layer;

g) exposing the second photoresist layer using a second mask; and

h) developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer,

i) wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately.

2. The method of claim 1 in which step e) comprises a bake at elevated temperature to cross-link the protection layer.

3. The method of claim 1 in which step e) includes promoting cross-linking in the protection layer by a catalyst provided from the first photoresist layer.

4. The method of claim 3 in which the catalyst provided by the first photoresist layer is an acid which diffuses into the protection layer.

5. The method of claim 1 in which the first photoresist is a photoresist adapted for patterning using electromagnetic radiation in the UV spectrum below 200 nm.

6. The method of claim 1 in which the first photoresist comprises acrylates.

7. The method of claim 1 further including, after step e) and prior to step f), removing parts of the protection layer unchanged by step e).

8. The method of claim 1 applied in the fabrication of a device structure, in which the first mask is adapted to define horizontal features in a device and in which the second mask is adapted to define vertical features in the device, the horizontal and vertical features being defined in the same device layer and intersecting at selected locations.

9. The method of claim 1 applied in the fabrication of a device structure, in which the first mask is configured to define a first group of periodic features having a first spatial frequency and in which the second mask is configured to define a second group of periodic features having a second spatial frequency, wherein the first and second masks are registered relative to one another so as to result in features of the first and second groups together being defined at a third spatial frequency higher than the first or second spatial frequencies.

10. The method of claim 1 , wherein the step of coating the substrate with the second photoresist layer includes coating the protective layer and first photoresist layer.

11. The method of claim 1 , further including a step of applying a second protective layer on the second photoresist pattern to achieve the same dimensions as the first photoresist layer and protective layer.

12. A method of forming a pattern in at least one device layer in or on a substrate comprising, in the fabrication of a finFET structure, the steps of:

coating the device layer with a first photoresist layer;

exposing the first photoresist using a first mask configured and arranged to define the fins of a finFET;

developing the first photoresist layer to form a first pattern on the substrate;

coating the substrate with a protection layer;

treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render at least a portion of the changed protection layer immune to a subsequent exposure and/or developing step;

coating the substrate with a second photoresist layer;

exposing the second photoresist layer using a second mask configured and arranged to define common source regions and common drain regions interconnecting the fins in the same device layer; and

developing the second photoresist layer to form a second pattern on the substrate,

wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately.

13. The method of claim 12 in which the first mask is configured to define fins for multiple finFET devices with fins for multiple devices maintaining a substantially constant pitch both within individual devices and between adjacent devices.

14. The method of claim 13 in which the second mask is configured to provide breaks in the common source regions and/or the common drain regions at selected locations where fins are not required in the finFET devices, so as to prevent interconnection to fins at those selected locations.

15. A method of forming a pattern in at least one device layer in or on a substrate comprising, in the fabrication of a finFET structure, the steps of:

coating the device layer with a first photoresist layer;

exposing the first photoresist using a first mask configured and arranged to define a first group of fins of a finFET;

developing the first photoresist layer to form a first pattern on the substrate;

coating the substrate with a protection layer;

treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render at least a portion of the changed protection layer immune to a subsequent exposure and/or developing step;

coating the substrate with a second photoresist layer;

exposing the second photoresist layer using a second mask configured and arranged to define a second group of fins of a finFET, the first and second sets of fins being interspersed; and

developing the second photoresist layer to form a second pattern on the substrate,

wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately.

16. The method of claim 15 in which the first group of fins and the second group of fins are interleaved in an alternating pattern.

17. The method of claim 16 in which the fins in the first group are separated by a first pitch distance, the fins in the second group are also separated by a first pitch distance and the combined fins of the first and second groups are separated by a second pitch distance of approximately half the first pitch distance.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
PATENT RELEASE Recorded Apr 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.; MIZUHO BANK, LTD.
To: NXP B.V.
Reel/Frame 038400/0637 →
CERTIFICATE RE. TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Apr 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.; MIZUHO BANK, LTD.
To: NXP B.V.
Reel/Frame 038401/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2016
From: NXP B.V.
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 037973/0107 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2009
From: VANLEENHOVE, ANJA MONIQUE; VAN STEENWINCKEL, DAVID; VAN DAL, MARK; DOORNBOS, GERBEN; JUFFERMANS, CASPER; DIRKSEN, PETER
To: NXP, B.V.
Reel/Frame 022681/0121 →
Priority Claims (1)
EP 06124035 · Nov 14, 2006 · regional
Continuity (1)
Related Publication 20100028809A1 · Feb 4, 2010