Methods and structures for controlling wafer curvature
View Patent ↗Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
1. A method, comprising:
forming multiple wiring levels on a wafer from a first wiring level nearest said wafer to a last wiring level, each wiring level of said of multiple wiring levels comprising respective damascene wires in a respective interlevel dielectric layer having a top surface that is coplanar with a top surface of said respective damascene wire;
forming a dielectric passivation layer on said last wiring level of said multiple wiring levels and a polyimide layer on said passivation layer, said polyimide layer in internal tensile stress; and
wherein a compensating dielectric layer formed above said first wiring level is in internal compressive stress.
2. The method of claim 1 , wherein said compensating dielectric layer that is in internal compressive stress is said passivation layer.
3. The method of claim 2 , wherein said passivation layer comprises a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of plasma enhanced chemical-vapor-deposited fluoro-silicate glass and said internal compressive stress of said passivation layer is between about −0.03E10 dynes/cm 2 and about −0.20E10 dynes/cm 2 .
4. The method of claim 2 , wherein said passivation layer consists of a layer of high-density chemical-vapor-deposited silicon oxide and said internal compressive stress of said passivation layer is between about −0.10E10 dynes/cm 2 and about −0.30E10 dynes/cm 2 .
5. The method of claim 2 , wherein said passivation layer comprises a layer of plasma enhanced chemical-vapor-deposited silicon nitride and said internal compressive stress of said passivation layer is between about −0.07E10 dynes/cm 2 and about −03.E10 dynes/cm 2 .
6. The method of claim 1 , wherein said compensating dielectric layer that is in internal compressive stress is an upper dielectric layer of an interlevel dielectric layer of said one or more of said interlevel dielectric layers that comprises said upper dielectric layer on a lower dielectric layer.
7. The method of claim 6 , wherein said upper dielectric layer is formed in said last wiring level and top surfaces of wires in said last wiring level are coplanar with a top surface of said upper dielectric layer.
8. The method of claim 7 , further including:
forming an additional upper dielectric layer in an intermediate interlevel dielectric layer between said first wiring level and said last wiring level; and
wherein top surfaces of wires in said intermediate wiring level are coplanar with a top surface of said upper dielectric layer.
9. The method of claim 8 , wherein said additional upper dielectric layer is selected from the group consisting of (i) a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of plasma enhanced chemical-vapor-deposited fluoro-silicate glass, (ii) a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of high-density chemical-vapor-deposited silicon oxide, and (iii) a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of plasma enhanced chemical-vapor-deposited silicon nitride; and
said internal compressive stress of said passivation layer is between about −0.03E10 dynes/cm 2 and about −0.30E10 dynes/cm 2 .
10. The method of claim 6 , wherein said upper dielectric layer is formed in an intermediate interlevel dielectric layer between said first wiring level and said last wiring level and top surfaces of wires in said intermediate wiring level are coplanar with a top surface of said upper dielectric layer.
11. The method of claim 6 , wherein said upper dielectric layer is selected from the group consisting of (i) a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of plasma enhanced chemical-vapor-deposited fluoro-silicate glass, (ii) a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of high-density chemical-vapor-deposited silicon oxide, and (iii) a layer of plasma enhanced chemical-vapor-deposited silicon oxide, a layer of plasma enhanced chemical-vapor-deposited tetraethoxysilane oxide and a layer of plasma enhanced chemical-vapor-deposited silicon nitride; and
said internal compressive stress of said passivation layer is between about −0.03E10 dynes/cm 2 and about −0.30E10 dynes/cm 2 .
12. The method of claim 1 , wherein said polyimide layer has a thickness greater than about 10 microns.
13. The method of claim 1 , wherein said wafer maintains an absolute radius of curvature is greater than about 25 meters after said forming said polyimide layer.
14. The method of claim 1 , wherein said damascene wires of said last wiring level are thicker than damascene wires of other wiring levels of said multiple wiring levels.
15. The method of claim 1 , wherein said damascene wires of said last wiring level are dual-damascene wires having a wire portion and a via portion, said dual damascene wires are comprised of copper, and said wire regions of said dual-damascene wires have a thickness of about 6 microns or more.
16. The method of claim 1 , wherein said damascene wires of said last wiring level are dual-damascene wires having a wire portion and a via portion, said dual damascene wires are comprised of aluminum/copper, and said wire regions of said dual-damascene wires have a thickness of about 4 microns or more.
17. A structure, comprising:
multiple wiring levels on a wafer from a first wiring level nearest said wafer to a last wiring level, each wiring level of said of multiple wiring levels comprising respective damascene wires in a respective interlevel dielectric layer having a top surface that is coplanar with a top surface of said respective damascene wire;
a dielectric passivation layer on said last wiring level of said multiple wiring levels and a polyimide layer on said passivation layer, said polyimide layer in internal tensile stress; and
a compensating dielectric layer formed above said first wiring level, said compensating dielectric layer in internal compressive stress.
18. The structure of claim 17 , wherein said compensating dielectric layer that is in internal compressive stress is said passivation layer.
19. The structure of claim 18 , wherein said passivation layer comprises a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of fluoro-silicate glass and said internal compressive stress of said passivation layer is between about −0.03E10 dynes/cm 2 and about −0.20E10 dynes/cm 2 .
20. The structure of claim 18 , wherein said passivation layer consists of a layer of high-density silicon oxide and said internal compressive stress of said passivation layer is between about −0.10E10 dynes/cm 2 and about −0.30E10 dynes/cm 2 .
21. The structure of claim 18 , wherein said passivation layer comprises a layer of silicon nitride and said internal compressive stress of said passivation layer is between about −0.07E10 dynes/cm 2 and about −03.E10 dynes/cm 2 .
22. The structure of claim 17 , wherein said compensating dielectric layer that is in internal compressive stress is an upper dielectric layer of an interlevel dielectric layer of said one or more of said interlevel dielectric layers that comprises said upper dielectric layer on a lower dielectric layer.
23. The structure of claim 22 , wherein said upper dielectric layer is formed in said last wiring level and top surfaces of wires in said last wiring level are coplanar with a top surface of said upper dielectric layer.
24. The structure of claim 23 , further including:
forming an additional upper dielectric layer in an intermediate interlevel dielectric layer between said first wiring level and said last wiring level; and
wherein top surfaces of wires in said intermediate wiring level are coplanar with a top surface of said upper dielectric layer.
25. The structure of claim 24 , wherein said additional upper dielectric layer is selected from the group consisting of (i) a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of fluoro-silicate glass, (ii) a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of high-density silicon oxide, and (iii) a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of silicon nitride; and
said internal compressive stress of said passivation layer is between about −0.03E10 dynes/cm 2 and about −0.30E10 dynes/cm 2 .
26. The structure of claim 22 , wherein said upper dielectric layer is formed in an intermediate interlevel dielectric layer between said first wiring level and said last wiring level and top surfaces of wires in said intermediate wiring level are coplanar with a top surface of said upper dielectric layer.
27. The structure of claim 22 , wherein said upper dielectric layer is selected from the group consisting of (i) a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of fluoro-silicate glass, (ii) a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of high-density silicon oxide, and (iii) a layer of silicon oxide, a layer of tetraethoxysilane oxide and a layer of silicon nitride; and
said internal compressive stress of said passivation layer is between about −0.03E10 dynes/cm 2 and about −0.30E10 dynes/cm 2 .
28. The structure of claim 17 , wherein said polyimide layer has a thickness greater than about 29 microns.
29. The structure of claim 17 , wherein said wafer has an absolute radius of curvature greater than about 25 meters.
30. The structure of claim 17 , wherein said damascene wires of said last wiring level are thicker than damascene wires of other wiring levels of said multiple wiring levels.
31. The structure of claim 17 , wherein said damascene wires of said last wiring level are dual-damascene wires having a wire portion and a via portion, said dual damascene wires are comprised of copper, and said wire regions of said dual-damascene wires have a thickness of about 6 microns or more.
32. The structure of claim 17 , wherein said damascene wires of said last wiring level are dual-damascene wires having a wire portion and a via portion, said dual damascene wires are comprised of aluminum/copper, and said wire regions of said dual-damascene wires have a thickness of about 4 microns or more.