IP Library Granted Patent US 8,030,179
Granted Patent B2
US 8,030,179 · App. 12/556,408 · Granted Oct 4, 2011

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,030,179
App. No.
12/556,408
Granted
Oct 4, 2011
Kind
B2
Abstract

The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.

Claims (29)

1. A method of manufacturing a semiconductor device comprising:

forming first grooves on an upper face of a semiconductor wafer;

forming a first insulating layer that covers the upper face of the semiconductor wafer and side faces of the first grooves, and has second grooves that are formed in the first grooves and has concavities on side faces thereof,

forming first metal layers on side faces of the concavities; and

dividing the semiconductor wafer into a plurality of semiconductor chips by removing a bottom portion of the semiconductor wafer until the removal reaches bottom faces of the second grooves.

2. The method as claimed in claim 1 , wherein forming the first insulating layer includes:

forming an insulating film on the upper face of the semiconductor wafer; and

forming the second grooves that have the concavities formed in the insulating film.

3. The method as claimed in claim 2 , wherein:

forming the first insulating layer includes forming the first insulating layer that has openings on pad electrodes formed on the semiconductor wafer; and

forming the first metal layers includes forming the first metal layers that are formed on an upper face of the first insulating layer and are connected to the pad electrodes through the openings.

4. The method as claimed in claim 2 , wherein:

forming the first metal layers includes forming the first metal layers on an upper face of the first insulating layer; and

the method further includes forming a second insulating layer on upper faces of the first metal layers.

5. The method as claimed in claim 2 , wherein forming the first metal layers includes forming the first metal layers at center portions of inner side faces of the concavities.

6. The method as claimed in claim 2 , further comprising:

stacking a plurality of semiconductor chips that include at least one semiconductor chip divided from the semiconductor wafer; and

forming second metal layers in the concavities, the first metal layers being connected to the second metal layers.

7. The method as claimed in claim 6 , wherein forming the second metal layers includes forming the second metal layers by an electroless plating technique.

8. A method of manufacturing a semiconductor device comprising:

forming first grooves on an upper face of a semiconductor wafer;

forming a first insulating layer that covers the upper face of the semiconductor wafer and side faces of the first grooves, and has second grooves that are formed in the first grooves,

forming first metal layers on an upper face and side faces of the first insulating layer;

forming a second insulating layer that covers the upper face of the first insulating layer and side faces of the second grooves, and has third grooves that are formed in the second grooves and has concavities on side faces thereof, with the first metal layers being exposed through the concavities; and

dividing the semiconductor wafer into a plurality of semiconductor chips by removing a bottom portion of the semiconductor wafer until the removal reaches bottom faces of the third grooves.

9. The method as claimed in claim 8 , wherein:

forming the second insulating layer includes:

forming an insulating film on the semiconductor wafer; and

forming the third grooves that have the concavities formed in the insulating film.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0514 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2015
From: HOSHINO, MASATAKA; KASAI, JUNICHI; MEGURO, KOUICHI; FUKUYAMA, RYOTA; SHINMA, YASUHIRO; TAYA, KOJI; ONODERA, MASANORI; MASUDA, NAOMI
To: SPANSION LLC
Reel/Frame 034725/0381 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →