Non-volatile sonos-type memory device
View Patent ↗A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.
1. A method of fabricating a semiconductor device comprising the steps of:
forming assist gates on a gate insulating film on a semiconductor substrate of a chosen conductivity type;
forming a high-concentration impurity region in the semiconductor substrate and located predominantly between adjacent assist gates, the high-concentration impurity region having the same conductivity type as that of the semiconductor substrate, wherein portions of the high-concentration impurity region underlie the adjacent assist gates; and
forming a charge storage region above the semiconductor substrate and composed of at least a tunnel oxide film and a storage film.
2. The method as claimed in claim 1 , wherein the tunnel oxide film is formed with a thickness equal to or greater than 4 nm.
3. The method as claimed in claim 1 , wherein the tunnel oxide film is formed with a thickness equal to or greater than 5 nm.
4. The method as claimed in claim 1 , wherein the tunnel oxide film is formed with a thickness equal to or greater than 6 nm.
5. The method as claimed in claim 1 , wherein the tunnel oxide film is formed with a thickness equal to or greater than 7 nm.
6. The method as claimed in claim 1 , wherein the tunnel oxide film is formed with a thickness equal to or greater than 10 nm.
7. The method as claimed in claim 1 , further comprising a step of forming a top oxide film on the storage film, and wherein at least one of the tunnel oxide film and the top oxide film have a thickness equal to or greater than 5 nm.
8. The method as claimed in claim 1 , further comprising a step of forming a top oxide film on the storage film, and wherein at least one of the tunnel oxide film and the top oxide film have a thickness equal to or greater than 6 nm.
9. The method as claimed in claim 1 , further comprising a step of forming a top oxide film on the storage film, and wherein at least one of the tunnel oxide film and the top oxide film have a thickness equal to or greater than 7 nm.
10. The method as claimed in claim 1 , further comprising a step of forming a top oxide film on the storage film, and wherein at least one of the tunnel oxide film and the top oxide film have a thickness equal to or greater than 10 nm.
11. The method as claimed in claim 1 , wherein the tunnel oxide film has a thickness in which TN tunneling is dominant.
12. The method as claimed in claim 1 , further comprising a step of forming a substantially U-shaped recess in the semiconductor substrate and located between adjacent assist gates.
13. The method as claimed in claim 1 , further comprising forming sidewalls along sides of the assist gates.
14. The method as claimed in claim 13 , wherein the sidewalls are formed as part of the charge storage region, wherein the charge storage region is formed along the sides of the assist gates.
15. The method as claimed in claim 1 , wherein the charge storage region is formed below the assist gates.
16. The method as claimed in claim 1 , wherein the step of forming the charge storage region includes forming a gate insulating film below the assist gates.
17. The method as claimed in claim 1 , wherein the charge storage region is formed so as to cover the assist gates.