IP Library Granted Patent US 7,851,852
Granted Patent B2
US 7,851,852 · App. 12/574,934 · Granted Dec 14, 2010

Method of forming a low capacitance semiconductor device and structure therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,851,852
App. No.
12/574,934
Granted
Dec 14, 2010
Kind
B2
Abstract

In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Claims (12)

1. A semiconductor device comprising:

a substrate of a first conductivity type having a first surface;

a first source region of the first conductivity type on the first surface of the substrate;

a second source region of the first conductivity type on the first surface of the substrate wherein the second source region is spaced apart from the first source region;

a gate structure overlying the first surface of the substrate, the gate structure having a first end overlying an edge of the first source region, a second end overlying an edge of the second source region, the gate structure having a first surface substantially parallel to the first surface of the substrate and facing away from the first surface of the substrate;

a gate conductor of the gate structure overlying the substrate;

an insulator layer of the gate structure on the gate conductor;

a first conductor on the insulator layer; and

a source conductor formed on the first conductor subsequently to forming the first conductor.

2. The semiconductor device of claim 1 wherein the insulator layer is no thicker than about 10,000 Angstroms.

3. The semiconductor device of claim 1 wherein the first conductor includes doped polysilicon.

4. The semiconductor device of claim 1 wherein the first surface of the gate structure is devoid of an opening extending into the gate structure.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Mar 17, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024094/0429 →