IP Library Granted Patent US 8,318,549
Granted Patent B2
US 8,318,549 · App. 12/608,780 · Granted Nov 27, 2012

Molded semiconductor package having a filler material

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Quick Facts
Patent No.
US 8,318,549
App. No.
12/608,780
Granted
Nov 27, 2012
Kind
B2
Abstract

An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Claims (45)

1. A method of packaging an integrated circuit on a package substrate, comprising:

attaching the integrated circuit to the package substrate;

forming electrical connections between the integrated circuit and the package substrate using a first plurality of bond wires connected to a first plurality of bond posts on the package substrate and a first plurality of bond pads along a first side of the integrated circuit and a second plurality of bond wires connected to a second plurality of bond posts on the package substrate and a second plurality of bond pads along a second side of the integrated circuit; and

injecting mold compound through a plurality of openings in the package substrate, wherein a first opening of the plurality of openings is between the first plurality of bond posts and the first side and a second opening of the plurality of openings is between the second plurality of bond posts and the second side, wherein the injecting results in applying the mold compound over the integrated circuit and the package substrate, and wherein the plurality of wire bonds function to screen out a portion of filler from the mold compound during the injecting so that a first region of the mold compound has a first concentration of filler that is evenly distributed throughout an entirety of the first region, and a second region of the mold compound has a second concentration of filler that is evenly distributed throughout an entirety of the second region, the first concentration of filler being greater than the second concentration of filler, and wherein the first region includes all of the mold compound between the first and second plurality of wire bonds and the first and second sides to which the first and second plurality of wire bonds are adjacent, and the second region of the mold compound includes all of the mold compound between the first and second plurality of wire bonds and a mold cap boundary.

2. The method of claim 1 , wherein:

the step of forming further comprises using a third plurality of bond wires connected to a third plurality of bond posts on the package substrate and a third plurality of bond pads along a third side of the integrated circuit and a fourth plurality of bond wires connected to a fourth plurality of bond posts on the package substrate and a fourth plurality of bond pads along a fourth side of the integrated circuit; and

the step of injecting further comprises injecting the mold compound through a third opening of the plurality of openings wherein the third opening is between the third plurality of bond posts and the third side and through a fourth opening of the plurality of openings wherein the fourth opening is between the fourth plurality of bond posts and the fourth side.

3. The method of claim 1 , wherein the step of injecting further comprises injecting mold compound through a third opening of the plurality of openings wherein the third opening is between the first side and the first plurality of bond posts.

4. The method of claim 3 , wherein the third opening is a different size from the first opening.

5. The method of claim 4 , wherein the step of injecting comprises injecting the mold compound through a fifth opening of the plurality of openings wherein the fifth opening is between the first plurality of bond posts and the first side, through a sixth opening of the plurality of openings wherein the sixth opening is between the second plurality of bond posts and the second side, through a seventh opening of the plurality of openings wherein the seventh opening is between the third plurality of bond posts and the third side, and through an eighth opening of the plurality of openings wherein the eighth opening is between the fourth plurality of bond posts and the fourth side.

6. The method of claim 5 , wherein the step of injecting is further characterized as causing the molding compound located adjacent to the first side, the second side, the third side, and the fourth side and under the plurality of bond wires to have a higher concentration of the filler than the mold compound located above the plurality of wire bonds.

7. The method of claim 1 , wherein the mold compound comprises the filler and resin, wherein the step of injecting results in the plurality of wires causing a higher concentration of the filler below the plurality of wires than above the plurality of wires.

8. The method of claim 1 , wherein as the mold compound passes through the first and second openings during the step of injecting, the mold compound has a first concentration of the filler and has a second concentration greater than the first concentration adjacent to the first and second side after the step of injecting.

9. The method of claim 1 , wherein:

the first side terminates at a first corner and a second corner; and

the first opening is spaced away from the first corner and the second corner.

10. The method of claim 1 , wherein the step of injecting is further characterized by the first opening being of a different size than the second opening.

11. A packaged integrated circuit, comprising a package substrate;

an integrated circuit on a top surface of the package substrate, wherein the integrated circuit has a first side, a second side, a third side, and a fourth side;

a first plurality of wire bonds along the first side extending from the top surface of the package substrate to the integrated circuit;

a second plurality of wire bonds along the second side extending from the top surface of the package substrate to the integrated circuit; and

mold compound over the package substrate and the integrated circuit wherein a first region of the mold compound includes all of the mold compound between the first and second plurality of wire bonds and the first and second sides to which the first and second plurality of wire bonds are adjacent, and the first region of the mold compound has a first concentration of filler that is evenly distributed throughout an entirety of the first region, and a second region of the mold compound includes the mold compound between the first and second plurality of wire bonds and a mold cap boundary, and the second region of the mold compound has a second concentration of filler that is evenly distributed throughout an entirety of the second region, the first concentration of filler being greater than the second concentration of filler.

12. The packaged integrated circuit of claim 11 , wherein the package substrate has a plurality of openings in the package substrate filled with mold compound, wherein a first opening of the plurality of openings is adjacent to the first side and a second opening of the plurality of openings is adjacent to the second side.

13. The packaged integrated circuit of claim 11 , further comprising:

a third plurality of wire bonds along the third side extending from the top surface of the package substrate to the integrated circuit;

a fourth plurality of wire bonds along the fourth side extending from the top surface of the package substrate to the integrated circuit; and

mold compound over the package substrate and the integrated circuit wherein the mold compound under the third and fourth plurality of wire bonds adjacent to the third and fourth sides has a concentration of filler greater than that of the mold compound over the third and fourth plurality of wire bonds.

14. The packaged integrated circuit of claim 11 , further comprising:

a first plurality of bond posts on the package substrate coupled to the first plurality of wire bonds;

a second plurality of bond posts on the package substrate coupled to the second plurality of wire bonds;

a third plurality of bond posts on the package substrate coupled to the third plurality of wire bonds; and

a fourth plurality of bond posts on the package substrate coupled to the fourth plurality of wire bonds;

a first opening in the package substrate filled with mold compound located between the first side and the first plurality of bond posts;

a second opening in the package substrate filled with mold compound located between the second side and the second plurality of bond posts;

a third opening in the package substrate filled with mold compound located between the third side and the third plurality of bond posts; and

a fourth opening in the package substrate filled with mold compound located between the second side and the second plurality of bond posts.

15. The packaged integrated circuit of claim 12 , wherein the first opening has a different size from the second opening.

16. The packaged integrated circuit of claim 12 , further comprising

a third opening in the package substrate filled with mold compound located between the first side and the first plurality of bond posts.

17. The packaged integrated circuit of claim 16 , wherein the first opening has a different size from the third opening.

18. A method of forming mold compound over an integrated circuit attached to a top surface of a package substrate, comprising:

attaching bond wires between the package substrate and along each side of the integrated circuit;

forming a plurality of openings in the package substrate under the wire bonds, wherein each side of the integrated circuit has at least one opening of the plurality of openings adjacent thereto; and

injecting mold compound through the plurality of openings, wherein the plurality of wire bonds function to screen out a portion of filler from the mold compound during the injecting so that a first region of the mold compound has a first concentration of filler that is evenly distributed throughout an entirety of the first region, and a second region of the mold compound has a second concentration of filler that is evenly distributed throughout an entirety of the second region, the first concentration of filler being greater than the second concentration of filler, and wherein the first region includes all of the mold compound between the first and second plurality of wire bonds and the first and second sides to which the first and second plurality of wire bonds are adjacent, and the second region of the mold compound includes all of the mold compound between the first and second plurality of wire bonds and a mold cap boundary.

19. The method of claim 18 , wherein the step of injecting is further characterized as causing mold compound to form over the integrated circuit and the package substrate so that a first concentration of the filler of the mold compound adjacent to each side of the integrated circuit and under the bond wires is greater than a second concentration of the filler of the mold compound over the bond wires.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2018
From: NXP USA, INC.
To: VLSI TECHNOLOGY LLC
Reel/Frame 045084/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024079/0082 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2009
From: HESS, KEVIN J.; LEE, CHU-CHUNG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 023444/0967 →