Method of fabricating a self-aligning damascene memory structure

1. A method of forming a memory cell, the method comprising:

forming a first pillar-shaped element comprising a first semiconductor material;

forming a first mold comprising an opening self-aligned with the first pillar-shaped element; and

depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element.

2. The method of claim 1 , wherein forming the first pillar shaped element comprises:

depositing the first semiconductor material over a conductor;

depositing a first sacrificial material over the first semiconductor material; and

patterning and etching the first semiconductor material and the first sacrificial material to form the first pillar shaped element.

3. The method of claim 2 , wherein the first sacrificial material comprises a dielectric material.

4. The method of claim 2 , wherein the first sacrificial material comprises Si 3 N 4 .

5. The method of claim 1 , wherein the first semiconductor material comprises N-type semiconductor material.

6. The method of claim 1 , further comprising doping the second pillar shaped element to form a P-type region.

7. The method of claim 1 , wherein the first semiconductor material comprises P-type semiconductor material, and wherein the method further comprises doping the second pillar shaped element to form an N-type region.

8. The method of claim 1 , wherein the first pillar-shaped element comprises first sacrificial material, and wherein forming the first mold comprises:

depositing an insulating material on the first pillar-shaped element; and

removing the first sacrificial material to form the opening in the mold.

9. The method of claim 8 , wherein the insulating material comprises one or more of silicon oxide, silicon dioxide and silicon oxynitride.

10. The method of claim 8 , wherein the insulating material comprises a high density plasma silicon dioxide.

11. The method of claim 1 , further comprising forming a second mold comprising a trench self-aligned with the second pillar shaped element.

12. The method of claim 11 , wherein forming the second mold comprises:

depositing a second sacrificial material over the second pillar shaped element;

patterning and etching the second sacrificial material to form rails of the second sacrificial material.

13. The method of claim 12 , further comprising:

depositing an insulating material on the rails of the second sacrificial material; and

removing the rails of the second sacrificial material to form the trench.

14. The method of claim 13 , further comprising filling the trench with conductive material to form a conductor.

15. A memory cell formed according to the method of claim 1 .

16. An array of memory cells formed according to the method of claim 1 .

17. A three-dimensional array of memory cells formed according to the method of claim 1 .

18. A method of forming an array of memory cells, the method comprising:

forming a plurality of first pillar-shaped elements, each comprising a first semiconductor material;

forming a first mold comprising a plurality of openings, each opening self-aligned with a respective first pillar-shaped element; and

depositing a second semiconductor material in the openings to form a plurality of second pillar-shaped elements, each second pillar-shaped element above a respective first pillar-shaped element.

19. The method of claim 18 , wherein forming the first pillar shaped elements comprises:

depositing the first semiconductor material over a conductor;

depositing a first sacrificial material over the first semiconductor material; and

patterning and etching the first semiconductor material and the first sacrificial material to form the first pillar shaped elements.

20. The method of claim 19 , wherein the first sacrificial material comprises a dielectric material.

21. The method of claim 19 , wherein the first sacrificial material comprises Si 3 N 4 .

22. The method of claim 18 , wherein the first semiconductor material comprises N-type semiconductor material.

23. The method of claim 18 , further comprising doping the second pillar shaped elements to form a plurality of P-type regions.

24. The method of claim 18 , wherein the first semiconductor material comprises P-type semiconductor material, and wherein the method further comprises doping the second pillar shaped elements to form a plurality of N-type regions.

25. The method of claim 18 , wherein the first pillar-shaped elements each comprise first sacrificial material, and wherein forming the first mold comprises:

depositing an insulating material on the first pillar-shaped elements; and

removing the first sacrificial material to form the openings in the mold.

26. The method of claim 25 , wherein the insulating material comprises one or more of silicon oxide, silicon dioxide and silicon oxynitride.

27. The method of claim 25 , wherein the insulating material comprises a high density plasma silicon dioxide.

28. The method of claim 18 , further comprising forming a second mold comprising a plurality of trenches, each trench self-aligned with a respective second pillar shaped element.

29. The method of claim 28 , wherein forming the second mold comprises:

depositing a second sacrificial material over the second pillar shaped elements;

patterning and etching the second sacrificial material to form rails of the second sacrificial material.

30. The method of claim 29 , further comprising:

depositing an insulating material on the rails of the second sacrificial material; and

removing the rails of the second sacrificial material to form the trenches.

31. The method of claim 30 , further comprising filling the trenches with conductive material to form a plurality of conductors.

32. An array of memory cells formed according to the method of claim 18 .

33. A three-dimensional array of memory cells formed according to the method of claim 18 .