Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
View Patent ↗A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.
1. A method of making a semiconductor device, comprising:
forming a stress relief buffer by,
(a) forming a first compliant layer,
(b) forming a silicon layer over the first compliant layer, and
(c) forming a second compliant layer over the silicon layer;
providing a temporary substrate;
mounting a semiconductor die to the temporary substrate;
mounting the stress relief buffer to the temporary substrate around the semiconductor die;
depositing an encapsulant between the semiconductor die and stress relief buffer;
removing the temporary substrate; and
forming an interconnect structure over the semiconductor die, encapsulant, and stress relief buffer, the interconnect structure being electrically connected to the semiconductor die.
2. The method of claim 1 , further including forming the stress relief buffer in a location designated for bump formation.
3. The method of claim 1 , wherein the stress relief buffer includes a multi-layer composite material and structure with damping properties.
4. The method of claim 1 , further including forming a stiffener layer over the stress relief buffer and encapsulant.
5. The method of claim 1 , wherein the stress relief buffer is thinner than the semiconductor die.
6. The method of claim 1 , further including forming a circuit within the stress relief buffer.
7. A method of making a semiconductor device, comprising:
providing a temporary substrate;
mounting a semiconductor die or component to the temporary substrate;
preforming a stress relief layer;
placing the stress relief layer over the temporary substrate after mounting a semiconductor die or component to the temporary substrate, the stress relief layer being disposed around the semiconductor die or component and spaced apart from the semiconductor die or component;
depositing an encapsulant over the stress relief buffer and semiconductor die or component;
removing the temporary substrate;
forming an interconnect structure over the semiconductor die or component and stress relief layer, the interconnect structure being electrically connected to the semiconductor die or component; and
singulating the semiconductor device through the stress relief layer and encapsulant so that the stress relief layer is exposed from a side surface of the semiconductor device.
8. The method of claim 7 , further including forming a stiffener layer over the stress relief buffer and encapsulant.
9. The method of claim 7 , wherein the stress relief layer is thinner than the semiconductor die or component.
10. The method of claim 7 , further including forming a circuit layer within the stress relief buffer.
11. A method of making a semiconductor device, comprising:
providing a temporary substrate;
mounting a semiconductor die or component to the temporary substrate;
mounting a stress relief buffer to the temporary substrate by,
(a) forming a first compliant layer,
(b) forming a stiff layer over the first compliant layer, and
(c) forming a second compliant layer over the stiff layer; and
depositing an encapsulant between the stress relief buffer and semiconductor die or component.
12. The method of claim 11 , further including:
removing the temporary substrate; and
forming an interconnect structure over the semiconductor die or component and stress relief buffer, the interconnect structure being electrically connected to the semiconductor die or component.
13. The method of claim 11 , further including forming the stress relief buffer in a location designated for bump formation.
14. The method of claim 11 , wherein the stress relief buffer includes a multi-layer composite material.
15. The method of claim 11 , further including forming a stiffener layer over the stress relief buffer and encapsulant.
16. The method of claim 11 , wherein the stress relief buffer is thinner than the semiconductor die or component.
17. The method of claim 11 , further including forming a circuit layer within the stress relief buffer.
18. A method of making a semiconductor device, comprising:
providing a semiconductor die or component;
preforming a stress relief layer;
disposing the stress relief layer around the semiconductor die or component and spaced apart from the semiconductor die or component;
depositing an encapsulant over the stress relief buffer and semiconductor die or component;
forming an interconnect structure over the semiconductor die or component and stress relief layer, the interconnect structure being electrically connected to the semiconductor die or component; and
singulating the semiconductor device through the stress relief layer and encapsulant so that the stress relief layer is exposed from a side surface of the semiconductor device.
19. The method of claim 18 , further including forming the stress relief buffer in a location designated for bump formation.
20. The method of claim 18 , wherein the stress relief buffer includes a multi-layer composite material and structure with damping properties.
21. The method of claim 18 , wherein forming the stress relief buffer includes:
forming a first compliant layer;
forming a silicon layer over the first compliant layer; and
forming a second compliant layer over the silicon layer.
22. The method of claim 18 , further including forming a stiffener layer over the stress relief buffer and encapsulant.
23. The method of claim 18 , wherein the stress relief buffer is thinner than the semiconductor die or component.
24. The method of claim 18 , further including forming a circuit within the stress relief buffer.