Integrated circuit packaging system with interconnect and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a first substrate external layer having an opening;

forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the first substrate external layer;

forming an insulation layer over the first substrate external layer and the convex interconnect;

forming a horizontal conductive pathway on the insulation layer;

forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect, the single interlayer conductive connector through the horizontal conductive pathway and the insulation layer;

forming a second substrate external layer over the single interlayer conductive connector, the second substrate external layer having a hole exposing the horizontal conductive pathway; and

connecting an integrated circuit and the horizontal conductive pathway with the integrated circuit over the second substrate external layer.

2. The method as claimed in claim 1 wherein forming the single interlayer conductive connector includes forming the single interlayer conductive connector from the horizontal conductive pathway to the horizontal flange.

3. The method as claimed in claim 1 wherein forming the single interlayer conductive connector includes forming the single interlayer conductive connector from the horizontal conductive pathway to the protrusion.

4. The method as claimed in claim 1 further comprising:

mounting a device over the first substrate external layer; and

wherein forming the insulation layer over the first substrate external layer includes:

forming the insulation layer over the device.

5. A method of manufacture of an integrated circuit packaging system comprising:

providing a first substrate external layer having an opening;

forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the first substrate external layer;

forming an insulation layer over the first substrate external layer and the convex interconnect;

forming a horizontal conductive pathway on the insulation layer;

forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect, the single interlayer conductive connector through the horizontal conductive pathway and the insulation layer;

forming a second substrate external layer over the single interlayer conductive connector, the second substrate external layer having a hole exposing the horizontal conductive pathway; and

connecting an integrated circuit and the horizontal conductive pathway with the integrated circuit over the first substrate external layer and the second substrate external layer.

6. The method as claimed in claim 5 further comprising:

mounting a device over the first substrate external layer; and

wherein forming the insulation layer includes:

forming the insulation layer over the device.

7. The method as claimed in claim 5 further comprising:

mounting a component over the insulation layer; and

connecting a component conductive connector to the component and the horizontal conductive pathway.

8. The method as claimed in claim 5 further comprising dispensing an underfill between the second substrate external layer and the integrated circuit.

9. The method as claimed in claim 5 wherein connecting the integrated circuit includes connecting a flip chip.

10. An integrated circuit packaging system comprising:

a first substrate external layer having an opening;

a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the first substrate external layer;

an insulation layer over the first substrate external layer and the convex interconnect;

a horizontal conductive pathway on the insulation layer;

a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect, the single interlayer conductive connector through the horizontal conductive pathway and the insulation layer;

a second substrate external layer over the single interlayer conductive connector, the second substrate external layer having a hole exposing the horizontal conductive pathway; and

an integrated circuit connected to the horizontal conductive pathway with the integrated circuit over the second substrate external layer.

11. The system as claimed in claim 10 wherein the single interlayer conductive connector includes the single interlayer conductive connector from the horizontal conductive pathway to the horizontal flange.

12. The system as claimed in claim 10 wherein the single interlayer conductive connector includes the single interlayer conductive connector from the horizontal conductive pathway to the protrusion.

13. The system as claimed in claim 10 further comprising:

a device over the first substrate external layer; and

wherein:

the insulation layer is over the device.

14. The system as claimed in claim 10 wherein the integrated circuit is over the first substrate external layer.

15. The system as claimed in claim 14 further comprising:

a device over the first substrate external layer; and

wherein the insulation layer includes:

the insulation layer over the device.

16. The system as claimed in claim 14 further comprising:

a component over the insulation layer; and

a component conductive connector connected to the component and the horizontal conductive pathway.

17. The system as claimed in claim 14 further comprising an underfill between the second substrate external layer and the integrated circuit.

18. The system as claimed in claim 14 wherein the integrated circuit includes a flip chip.