IP Library Granted Patent US 8,304,286
Granted Patent B2
US 8,304,286 · App. 12/636,703 · Granted Nov 6, 2012

Integrated circuit packaging system with shielded package and method of manufacture thereof

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,304,286
App. No.
12/636,703
Granted
Nov 6, 2012
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material.

Claims (36)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate assembly having a connection path;

mounting a base device over the substrate assembly with a mount layer;

mounting a stack device over the base device and having a stack die and a stack-organic-material;

forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and

applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material.

2. The method as claimed in claim 1 wherein forming the stack-through-via includes forming the stack-through-via partially exposed from the stack-organic-material.

3. The method as claimed in claim 1 further comprising applying a horizontal barrier around the base device.

4. The method as claimed in claim 1 further comprising attaching a conductive bump on the stack-through-via.

5. The method as claimed in claim 1 wherein mounting the base device includes forming a base-through-via in the base device.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate assembly having a connection path;

mounting a base device over the substrate assembly with a mount layer;

mounting a stack device over the base device and having a stack die and a stack-organic-material;

forming a stack-through-via in a the stack-organic-material of the stack device and connected to the stack die and the substrate assembly;

applying an encapsulant over the base device and the stack device; and

applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material.

7. The method as claimed in claim 6 wherein forming the stack-through-via includes forming the stack-through-via partially exposed from the stack-organic-material and sides of the stack device.

8. The method as claimed in claim 6 further comprising applying a horizontal barrier around the stack die.

9. The method as claimed in claim 6 further comprising attaching a conductive bump on the stack-through-via and substantially exposed from the encapsulant.

10. The method as claimed in claim 6 wherein mounting the base device includes forming a base-through-via in a base-organic-material of the base device.

11. An integrated circuit packaging system comprising:

a substrate assembly having a connection path;

a base device over the substrate assembly with a mount layer;

a stack device over the base device and having a stack die and a stack-organic-material;

a stack-through-via formed in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and;

a shield layer directly on the stack-through-via having a substantially flat surface characteristic of a planarization process and partially exposed from the stack-organic-material.

12. The system as claimed in claim 11 wherein the stack-through-via is formed partially exposed from the stack-organic-material.

13. The system as claimed in claim 11 further comprising a horizontal barrier around the base device.

14. The system as claimed in claim 11 further comprising a conductive bump on the stack-through-via.

15. The system as claimed in claim 11 wherein the base device includes a base-through-via.

16. The system as claimed in claim 11 further comprising an encapsulant applied over the base device and the stack device.

17. The system as claimed in claim 16 wherein the stack-through-via is partially exposed from the stack-organic-material and sides of the stack device.

18. The system as claimed in claim 16 further comprising a horizontal barrier around the base device or the stack die.

19. The system as claimed in claim 16 further comprising a conductive bump on the stack-through-via and substantially exposed from the encapsulant.

20. The system as claimed in claim 16 wherein the base device includes a base-through-via in a base-organic-material of the base device.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0252. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0784 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0252 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2010
From: PAGAILA, REZA ARGENTY; MERILO, DIOSCORO A.; HUANG, SHUANGWU
To: STATS CHIPPAC LTD.
Reel/Frame 024441/0220 →
Continuity (1)
Related Publication 20110140247A1 · Jun 16, 2011