IP Library Granted Patent US 8,516,290
Granted Patent B1
US 8,516,290 · App. 12/698,752 · Granted Aug 20, 2013

Clocking scheme for bridge system

Inventor: Christopher Thomas (San Diego, CA)
Assignee: SMSC Holdings S.A.R.L.
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Quick Facts
Patent No.
US 8,516,290
App. No.
12/698,752
Granted
Aug 20, 2013
Kind
B1
Abstract

Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to transmit and receive data to and from a host device in accordance with a first protocol. A synchronous second interface is adapted to transmit and receive data to and from a device external to the host device in accordance with a second protocol. A bridge controller is adapted to convert the data received from the host device from the first protocol to the second protocol for transmission to the external device. A clock and data recovery (CDR) block is adapted to recover a clock signal from the first interface to synchronize the data received from the host device. The second interface is adapted to synchronize the converted second protocol data transmitted to the external device using the recovered clock signal.

Claims (53)

1. A system comprising:

an asynchronous first interface which transmits and receives data to and from a host device in accordance with a first protocol;

a synchronous second interface which transmits and receives data to and from a device external to the host device in accordance with a second protocol;

a bridge controller which converts the data received from the host device from the first protocol to the second protocol for transmission to the external device;

a clock and data recovery (CDR) block which recovers a clock signal from the first interface to synchronize the data received from the host device;

a delay block which delays the recovered clock signal to synchronize the data received from the external device; and

wherein the second interface synchronizes the converted second protocol data transmitted to the external device using the recovered clock signal.

2. The system of claim 1 , wherein the first interface is a Universal Serial Bus (USB) 3.0 interface and the second interface is a Peripheral Component Interface Express (PCIe) interface.

3. The system of claim 1 , wherein:

the bridge controller is further adapted to convert the data received from the external device from the second protocol to the first protocol for transmission to the host device; and

the first interface is adapted to synchronize the converted first protocol data transmitted to the host device using the recovered clock signal.

4. The system of claim 3 , wherein the external device is a first external device, the system further comprising:

a third interface adapted to transmit and receive data to and from a second device external to the host device in accordance with the second protocol;

wherein the bridge controller is adapted to convert the data received from the second external device from the second protocol to the first protocol to provide additional converted first protocol data for transmission to the host device; and

wherein the third interface is adapted to synchronize the converted second protocol data transmitted to the second external device using the recovered clock signal.

5. The system of claim 4 , wherein:

the second and third interfaces are adapted to be selectively configured by the bridge controller to operate in accordance with either the first protocol or the second protocol; and

the system is adapted to operate as a hub for the host device when the second and third interfaces are configured to operate in accordance with the first protocol.

6. The system of claim 1 , wherein the second interface is adapted to be selectively configured by the bridge controller to operate in accordance with either an asynchronous protocol or a synchronous protocol, wherein the second interface comprises at least a pair of pins adapted to:

transmit and receive differential data signals to and from the external device when the second interface is configured to operate in accordance with the asynchronous protocol; and

transmit the recovered clock signal as a differential clock signal when the second interface is configured to operate in accordance with the synchronous protocol.

7. A method comprising:

receiving data from a host device at an asynchronous first interface in accordance with a first protocol;

recovering a clock signal from the first interface to synchronize the data received from the host device;

converting the data received from the host device from the first protocol to a second protocol;

passing the converted second protocol data to a synchronous second interface;

transmitting the converted second protocol data from the second interface to a device external to the host device in accordance with the second protocol;

delaying the recovered clock signal; and

synchronizing the converted second protocol data transmitted to the external device using the recovered clock signal.

8. The method of claim 7 , wherein the first interface is a Universal Serial Bus (USB) 3.0 interface and the second interface is a Peripheral Component Interface Express (PCIe) interface.

9. The method of claim 7 , further comprising:

synchronizing the data received from the external device using the delayed recovered clock signal.

10. The method of claim 7 , further comprising:

receiving data from the external device at the second interface in accordance with the second protocol;

converting the data received from the external device from the second protocol to the first protocol;

passing the converted first protocol data to the first interface;

transmitting the converted first protocol data from the first interface to the host device in accordance with the first protocol; and

synchronizing the converted first protocol data transmitted to the host device using the recovered clock signal.

11. The method of claim 10 , wherein the external device is a first external device, the method further comprising:

transmitting the converted second protocol data from a third interface to a second device external to the host device in accordance with the second protocol;

synchronizing the converted second protocol data transmitted to the second external device using the recovered clock signal;

receiving data from the second external device at the third interface in accordance with the second protocol;

converting the data received from the second external device from the second protocol to the first protocol to provide additional converted first protocol data;

passing the additional converted first protocol data to the first interface;

transmitting the additional converted first protocol data from the first interface to the host device in accordance with the first protocol; and

synchronizing the additional converted first protocol data transmitted to the host device using the recovered clock signal.

12. The method of claim 11 , further comprising:

selectively configuring the second and third interfaces to operate in accordance with either the first protocol or the second protocol; and

providing a hub for the host device using the second and third interfaces when the second and third interfaces are configured to operate in accordance with the first protocol.

13. The method of claim 7 , further comprising:

selectively configuring the second interface to operate in accordance with either an asynchronous protocol or a synchronous protocol;

transmitting and receiving differential data signals to and from the external device through at least a pair of pins of the second interface when the second interface is configured to operate in accordance with the asynchronous protocol; and

transmitting the recovered clock signal as a differential clock signal through the pins when the second interface is configured to operate in accordance with the synchronous protocol.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2011
From: SYMWAVE, INC.
To: SMSC HOLDINGS S.A.R.L.
Reel/Frame 026377/0519 →
SECURITY AGREEMENT Recorded Aug 13, 2010
From: SYMWAVE, INC.
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 024823/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2010
From: THOMAS, CHRISTOPHER
To: SYMWAVE, INC.
Reel/Frame 023887/0169 →