Semiconductor structures and methods of manufacturing the same

1. A method comprising:

etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material;

removing the liner material on a side of the implant; and

depositing stressor material in the undercut under the one or more gate structures.

2. The method of claim 1 , further comprising etching one or more recesses on sides of the one or more gate structures, prior to the etching of the undercut.

3. The method of claim 2 , wherein the etching of the undercut is a reactive ion etching process using dry etchants.

4. The method of claim 2 , wherein the etching of the undercut is a reactive ion etching process using wet etchants.

5. The method of claim 2 , wherein the one or more recesses has a depth ranging from about 1 nm to about 30 nm.

6. The method of claim 5 , further comprising forming the liner material after an extension implant and annealing process, wherein a vertical dimension of the liner material will control a distance of the undercut from the one or more gate structures.

7. The method of claim 6 , wherein the liner material is formed on a side of the implant and a portion of the substrate material.

8. The method of claim 7 , wherein the liner material is formed on a sidewall of the substrate material after the formation of the one or more recesses.

9. The method of claim 1 , further comprising forming a spacer material on sidewalls of the one or more gate structures.

10. The method of claim 9 , wherein the spacer material is different from the liner material and the removal of the liner material is performed by a selective etching to the spacer material.

11. A method comprising:

forming gate structures on a substrate;

forming extension implants in the substrate and under the gate structures;

forming spacers on the gate structures;

forming recesses in the substrate and on the sides of the gate structures;

forming a liner on sidewalls of the recesses, which protect the extension implants during subsequent processes;

etching an undercut in the substrate to underneath the gate structures;

removing the liner on the sidewalls of the recesses; and

depositing stressor material in the recesses and the undercut.

12. The method claim 11 , wherein the recesses are formed at a controllable depth, and the liner on the sidewalls of the recesses control a distance of the undercut from the gate structures.

13. The method of claim 12 , wherein the liner is of a different material than the spacers.

14. The method of claim 13 , wherein removing the liner is an etching process selective to the material of the spacer.

15. The method of claim 12 , wherein the liner is a same material as the spacers and the removing of the liner is performed by an etching process after a block material is deposited to protect the material of the spacers.

16. The method of claim 11 , wherein the stressor material is Si 1-x Ge X for a PFET and Si 1-x C X for an NFET.

17. The method of claim 11 , wherein the stressor material is deposited in the undercut at a distance from the gate structure controlled by a vertical distance of the liner.

18. The method of claim 11 , wherein the undercuts are formed by a wet etching process.

19. The method of claim 11 , wherein the undercuts are formed by a dry etching process.